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DSDATA2 数据表(PDF) 28 Page - Analog Devices

部件名 DSDATA2
功能描述  4 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

DSDATA2 数据表(HTML) 28 Page - Analog Devices

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AD1939
Data Sheet
Rev. E | Page 28 of 32
Table 25. ADC Control 2 Register
Bit
Value
Function
Description
0
0
50/50 (allows 32, 24, 20, or 16 bit clocks (BCLKs)
per channel)
LRCLK format
1
Pulse (32 BCLKs per channel)
1
0
Drive out on falling edge (DEF)
BCLK polarity
1
Drive out on rising edge
2
0
Left low
LRCLK polarity
1
Left high
3
0
Slave
LRCLK master/slave
1
Master
5:4
00
64
BCLKs per frame
01
128
10
256
11
512
6
0
Slave
BCLK master/slave
1
Master
7
0
ABCLK pin
BCLK source
1
Internally generated



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