AD7946

Rev. A | Page 19 of 24

CS MODE 4-WIRE, NO BUSY INDICATOR

This mode is usually used when multiple AD7946s are

connected to an SPI-compatible digital host.

A connection diagram example using two AD7946s is shown in

Figure 37, and the corresponding timing is given in Figure 38.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback (if SDI and CNV are low, SDO is

driven low). Prior to the minimum conversion time, SDI could

be used to select other SPI devices, such as analog multiplexers,

but SDI must be returned high before the minimum conversion

time and held high until the maximum conversion time to

avoid the generation of the BUSY signal indicator. When the

conversion is complete, the AD7946 enters the acquisition

phase and powers down. Each ADC result can be read by

bringing its SDI input low, which consequently outputs the MSB

onto SDO. The remaining data bits are then clocked by subse-

quent SCK falling edges. The data is valid on both SCK edges.

Although the rising edge can be used to capture the data, a

digital host using the SCK falling edge allows a faster reading

falling edge, or when SDI goes high, whichever is earlier, SDO

returns to high impedance and another AD7946 can be read.

DATA IN

CLK

CS1

CONVERT

CS2

DIGITAL HOST

CNV

SCK

SDO

SDI

AD7946

CNV

SCK

SDO

SDI

AD7946

Figure 37. CS Mode 4-Wire, No BUSY Indicator Connection Diagram

SDO

D13

D12

D11

D1

D0

SCK

12

3

26

27

28

CONVERSION

ACQUISITION

ACQUISITION

SDI(CS1)

CNV

D1

12

13

D0

D13

D12

15

16

14

SDI(CS2)

Figure 38. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing