CC2500-RTR1 datasheet(26/99 Pages) TI1

26 / 99 page

CC2500

SWRS040C

Page 26 of 89

The GDO0 pin can also be used for an on-chip

analog temperature sensor. By measuring the

voltage on the GDO0 pin with an external ADC,

the

temperature

can

calculated.

Specifications for the temperature sensor are

found in Section 4.7 on page 14.

With default PTEST register setting (0x7F) the

temperature sensor output is only available

when the frequency synthesizer is enabled

(e.g. the MANCAL, FSTXON, RX and TX

states).

It is necessary to write 0xBF to the

PTEST

sensor in the IDLE state. Before leaving the

IDLE state, the PTEST register should be

restored to its default value (0x7F).

11.3

Optional Radio Control Feature

The

CC2500 has an optional way of controlling

the radio, by reusing SI, SCLK and CSn from

the SPI interface. This feature allows for a

simple three-pin control of the major states of

the radio: SLEEP, IDLE, RX and TX.

This optional functionality is enabled with the

MCSM0.PIN_CTRL_EN

configuration bit.

State changes are commanded as follows:

When CSn is high the SI and SCLK is set to

the desired state according to Table 18. When

CSn

goes low the state of SI and SCLK is

latched and a command strobe is generated

internally according to the control coding. It is

only

possible

change

state

with

this

functionality. That means that for instance RX

will not be restarted if SI and SCLK are set to

RX and CSn toggles. When CSn is low the SI

and SCLK has normal SPI functionality.

All pin control command strobes are executed

immediately, except the SPWD strobe, which is

delayed until CSn goes high.

CSn

SCLK

Function

Chip unaffected by SCLK/SI



Generates SPWD strobe



Generates STX strobe



Generates SIDLE strobe



Generates SRX strobe

SPI

mode

SPI

mode

SPI mode (wakes up into

IDLE if in SLEEP/XOFF)

Table 18: Optional Pin Control Coding

12 Data Rate Programming

The data rate used when transmitting, or the

data rate expected in receive is programmed

the

MDMCFG3.DRATE_M

and

the

MDMCFG4.DRATE_E

configuration

registers.

The data rate is given by the formula below.

As the formula shows, the programmed data

rate depends on the crystal frequency.





XOSC

DRATE

DATA

DRATE







256

The following approach can be used to find

suitable values for a given data rate:

256

log



































DRATE

XOSC

DATA

XOSC

DATA

DRATE

If DRATE_M is rounded to the nearest integer

and becomes 256, increment DRATE_E and

use DRATE_M=0.

The data rate can be set from 1.2 kBaud to

500 kBaud with the minimum step size of:

Min Data

Rate

[kBaud]

Typical

Data Rate

[kBaud]

Max Data

Rate

[kBaud]

Data Rate

Step Size

[kBaud]

0.8

1.2/2.4

3.17

0.0062

3.17

4.8

6.35

0.0124

6.35

9.6

12.7

0.0248

12.7

19.6

25.4

0.0496

25.4

38.4

50.8

0.0992

50.8

76.8

101.6

0.1984

101.6

153.6

203.1

0.3967

203.1

250

406.3

0.7935

406.3

500

1.5869

Table 19: Data Rate Step Size

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