PCA9554_9554A

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Product data sheet

Rev. 9 — 19 March 2013

8 of 35

NXP Semiconductors

PCA9554; PCA9554A

6.1.4 Register 2 - Polarity Inversion register

This register allows the user to invert the polarity of the Input Port register data. If a bit in

this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in

this register is cleared (written with a ‘0’), the Input Port data polarity is retained.

6.1.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output. At reset, the

6.2 Power-on reset

reset condition is released and the PCA9554/PCA9554A registers and state machine will

device.

operating voltage.

Table 7.

Register 2 - Polarity Inversion register bit description

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

N7

R/W

0*

inverts polarity of Input Port register data

0 = Input Port register data retained (default value)

1 = Input Port register data inverted

6N6

R/W

0*

5N5

R/W

0*

4N4

R/W

0*

3N3

R/W

0*

2N2

R/W

0*

1N1

R/W

0*

0N0

R/W

0*

Table 8.

Register 3 - Configuration register bit description

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

C7

R/W

1*

configures the directions of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as input

(default value)

6C6

R/W

1*

5C5

R/W

1*

4C4

R/W

1*

3C3

R/W

1*

2C2

R/W

1*

1C1

R/W

1*

0C0

R/W

1*