PCF8536AT1 datasheet(34/74 Pages) NXP

34 / 74 page

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

34 of 74

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

8.6 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

8.7 Backplane outputs

The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane

output signals are generated based on the selected LCD multiplex drive mode.

• In 1:8 multiplex drive mode: BP0 to BP7 must be connected directly to the LCD.

• In 1:6 multiplex drive mode: BP0 to BP5 must be connected directly to the LCD.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

8.8 Segment outputs

The LCD drive section includes up to 44 segment outputs (S0 to S43) which must be

connected directly to the LCD. The segment output signals are generated based on the

multiplexed backplane signals and with data resident in the display register. When less

segment outputs are required, the unused segment outputs must be left open-circuit.

The number of available segments depends on the multiplex drive mode selected and the

number of GPOs used. The table shows consecutive GPOs selected, but this is just for

simplicity of explanation. Any combination of GPOs may be used.

Table 32.

Backplane and active segment combinations

Basic examples. GPO pins may be configured in any combination. Other LCD segment and GPO combinations are possible.

Multiplex

drive mode

Active BPs Active GPOs

None

GP0 only

GP0 to GP1 GP0 to GP2 GP0 to GP3 GP0 to GP4 GP0 to GP5

1:8

BP0 to BP7 S0 to S39

S1 to S39

S2 to S39

S3 to S39

S4 to S39

S5 to S39

S6 to S39

1:6

BP0 to BP5 S0 to S41

S1 to S41

S2 to S41

S3 to S41

S4 to S41

S5 to S41

S6 to S41

1:4

BP0 to BP3 S0 to S43

S1 to S43

S2 to S43

S3 to S43

S4 to S43

S5 to S43

S6 to S43

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