LTC1735CS datasheet(13/32 Pages) LINER

13 / 32 page

LTC1735

1735fc

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low

loss core material for toroids, but it is more expensive than

ferrite. A reasonable compromise from the same manu-

facturer is Kool M

µ. Toroids are very space efficient,

especially when you can use several layers of wire. Be-

cause they generally lack a bobbin, mounting is more

difficult. However, designs for surface mount are available

that do not increase the height significantly.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for use

with the LTC1735: An N-channel MOSFET for the top

(main) switch and an N-channel MOSFET for the bottom

(synchronous) switch.

The peak-to-peak gate drive levels are set by the INTVCC

voltage. This voltage is typically 5.2V during start-up (see

EXTVCC pin connection). Consequently, logic-level thresh-

old MOSFETs must be used in most LTC1735 applica-

tions. The only exception is when low input voltage is

expected (VIN < 5V); then, sub-logic level threshold

MOSFETs (VGS(TH) < 3V) should be used. Pay close

attention to the BVDSS specification for the MOSFETs as

well; many of the logic level MOSFETs are limited to 30V

or less.

Selection criteria for the power MOSFETs include the “ON”

resistance RDS(ON), reverse transfer capacitance CRSS,

input voltage and maximum output current. When the

LTC1735 is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

Main Switch Duty Cycle

OUT

Synchronous Switch Duty Cycle

OUT

–

APPLICATIO S I FOR ATIO

The MOSFET power dissipations at maximum output

current are given by:

MAIN

OUT

MAX

DS ON

MAX

RSS

() +

()

() ( )( )( )

()

SYNC

OUT

MAX

DS ON

() +

()

–

()

where

δ is the temperature dependency of RDS(ON) and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside

N-channel equation includes an additional term for transi-

tion losses, which are highest at high input voltages. For

VIN < 20V the high current efficiency generally improves

with larger MOSFETs, while for VIN > 20V the transition

losses rapidly increase to the point that the use of a higher

RDS(ON) device with lower CRSS actually provides higher

efficiency. The synchronous MOSFET losses are greatest

at high input voltage or during a short-circuit when the

duty cycle in this switch is nearly 100%.

The term (1 +

δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. CRSS is usually specified in the

MOSFET characteristics. The constant k = 1.7 can be

used to estimate the contributions of the two terms in the

main switch dissipation equation.

The Schottky diode D1 shown in Figure 1 conducts during the

dead-timebetweentheconductionofthetwopowerMOSFETs.

This prevents the body diode of the bottom MOSFET from

turning on and storing charge during the dead-time, which

could cost as much as 1% in efficiency. A 3A Schottky is

generally a good size for 10A to 12A regulators due to the

relatively small average current. Larger diodes can result in

additionaltransitionlossesduetotheirlargerjunctioncapaci-

tance. The diode may be omitted if the efficiency loss can be

tolerated.

LTC1735CS 数据表(PDF) 13 Page - Linear Technology

LTC1735CS 数据表(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载