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LTC1735CS 数据表(PDF) 24 Page - Linear Technology |
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LTC1735CS 数据表(HTML) 24 Page - Linear Technology |
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24 / 32 page ![]() 24 LTC1735 1735fc At full load current: VA A VA V V ITH MAX PP () •. / . . =+ + = − 15 5 2 0 084 0 3 177 At minimum load current: VA A VA V V ITH MIN PP () .• . / . . =+ + = − 02 2 2 0 084 0 3 040 In this circuit, VITH changes from 0.40V at light load to 1.77V at full load, a 1.37V change. Notice that ∆IL, the peak-to-peak inductor current, changes from light load to full load. Increasing the DC inductor current decreases the permeability of the inductor core material, which de- creases the inductance and increases ∆IL. The amount of inductance change is a function of the inductor design. To create the ±30mV input offset, the gain of the error amplifier must be limited. The desired gain is: A V Input Offset Error V V V ITH = ∆ == 137 20 03 22 8 . (. ) . Connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. The value of this resistor is: R A Error Amplifier g mS k ITH V m == = 22 8 13 17 54 . . . To center the output voltage variation, VITH must be centered so that no ITH pin current flows when the output voltage is nominal. VITH(NOM) is the average voltage be- tween VITH at maximum output current and minimum output current: V VV V VV VV ITH NOM ITH MAX ITH MIN ITH MIN () () ( ) () – .– . .. =+ =+ = 2 177 0 40 2 0 40 1 085 APPLICATIO S I FOR ATIO The Thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor R4 that sources current into the ITH pin and resistor R1 that sinks current to SGND. To calculate the resistor values, first determine the ratio between them: k VV V VV V INTVCC ITH NOM ITH NOM == = – .– . . . () () 52 1085 1 085 379 VINTVCC is equal to VEXTVCC or 5.2V if EXTVCC is not used. Resistor R4 is: Rk R k ITH 4 1 3 79 1 17 54 84 0 =+ = + = () • ( . ) • . . Resistor R1 is: R kR k k k ITH 1 1 3 79 1 17 54 379 22 17 = + = + = () • ( . ) • . . . Unfortunately, PCB noise can add to the voltage developed across the sense resistor, R5, causing the ITH pin voltage to be slightly higher than calculated for a given output current. The amount of noise is proportional to the output current level. This PCB noise does not present a serious problem but it does change the effective value of R5 so the calculated values of R1 and R4 may need to be adjusted to achieve the required results. Since PCB noise is a function of the layout, it will be the same on all boards with the same layout. Figures 9 and 10 show the transient response before and after active voltage positioning is implemented. Notice that active voltage positioning reduced the transient re- sponse from almost 200mVP-P to a little over 100mVP-P. Refer to Design Solutions 10 for more information about active voltage positioning. |
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