QUICC

MC68360

CE (ENABLE)

OE (OUTPUT ENABLE)

WE (WRITE)

DATA

ADDRESS

8-BIT BOOT

EPROM

(FLASH OR REGULAR)

CS0

OE

WE0

DATA

ADDRESS

RAS

CAS3–CAS0

W (WRITE)

DATA

ADDRESS

PARITY

16- OR 32-BIT

DRAM SIMM

(OPTIONAL PARITY)

RAS1

CAS3–CAS0

R/W

PRTY3–PRTY0

Figure 2. Minimum QUICC System Configuration

Figure 3 shows a larger system configuration. This system offers one EPROM, one flash EPROM, and

supports two DRAM SIMMs. Depending on the capacitance on the system bus, external buffers may be

required. From a logic standpoint, however, a glueless system is maintained.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com