ADL5372ACPZ-R21 datasheet(12/24 Pages) AD

12 / 24 page

ADL5372

Rev. 0 | Page 12 of 24

BASIC CONNECTIONS

Figure 25 shows the basic connections for the ADL5372.

VPS5

VPS3

VPS4

VPS2

VOUT

COM1

VPS1

COM1

VPS1

VOUT

C13

0.1µF

C11

OPEN

C12

0.1µF

CLON

100pF

C14

0.1µF

C15

0.1µF

C16

0.1µF

COUT

100pF

VPOS

QBBP

QBBN

IBBN

IBBP

EXPOSED PADDLE

CLOP

100pF

GND

F-MOD

Figure 25. Basic Connections for the ADL5372

Power Supply and Grounding

All the VPS pins must be connected to the same 5 V source.

Adjacent pins of the same name can be tied together and decoupled

with a 0.1 μF capacitor. These capacitors should be located as

close as possible to the device. The power supply can range

between 4.75 V and 5.25 V.

The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should

be tied to the same ground plane through low impedance paths.

The exposed paddle on the underside of the package should also

be soldered to a low thermal and electrical impedance ground

plane. If the ground plane spans multiple layers on the circuit

board, they should be stitched together with nine vias under the

exposed paddle. The Application Note AN-772 discusses the

thermal and electrical grounding of the LFCSP in detail.

Baseband Inputs

The baseband inputs QBBP, QBBN, IBBP, and IBBN must be

driven from a differential source. The nominal drive level of

1.4 V p-p differential (700 mV p-p on each pin) should be

biased to a common-mode level of 500 mV dc.

The dc common-mode bias level for the baseband inputs may

range from 400 mV to 600 mV. This results in a reduction in

the usable input ac swing range. The nominal dc bias of 500 mV

allows for the largest ac swing, limited on the bottom end by the

ADL5372 input range and on the top end by the output compliance

range on most DACs from Analog Devices.

LO Input

A single-ended LO signal should be applied to the LOIP pin

through an ac coupling capacitor. The recommended LO drive

power is 0 dBm. The LO return pin, LOIN, should be ac-coupled

to ground through a low impedance path.

The nominal LO drive of 0 dBm can be increased to up to 6 dBm

to realize an improvement in the noise performance of the

modulator. This improvement is tempered by degradation in

the sideband suppression performance (see Figure 20) and,

therefore, should be used judiciously. If the LO source cannot

provide the 0 dBm level, then operation at a reduced power

below 0 dBm is acceptable. Reduced LO drive results in slightly

increased modulator noise. The effect of LO power on sideband

suppression and carrier feedthrough is shown in Figure 20. The

effect of LO power on GSM noise is shown in Figure 35.

RF Output

The RF output is available at the VOUT pin (Pin 13). The

VOUT pin connects to an internal balun, which is capable of

driving a 50 Ω load. For applications requiring 50 Ω output

impedance, external matching is needed (see Figure 8 for S22

performance). The internal balun provides a low dc path to

ground. In most situations, the VOUT pin should be ac-coupled

to the load.

ADL5372ACPZ-R21 数据表(PDF) 12 Page - Analog Devices

ADL5372ACPZ-R21 数据表(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载

链接网址

ADL5372ACPZ-R21 数据表(PDF) 12 Page - Analog Devices

ADL5372ACPZ-R21 数据表(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表 下载

链接网址

数据表下载