ADE7912 datasheet(21/44 Pages) AD

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Data Sheet

ADE7912/ADE7913

Rev. 0 | Page 21 of 44

takes for the temperature sensor measurement to settle after the

TEMP_EN bit is set to 1 is 5 ms.

The expression used to calculate the temperature in the

microcontroller is:

temp =

8.72101 × 10−5 × (V2WV + TEMPOS × 211) − 306.47

where:

temp is the temperature value measured in degrees Celsius. The

gain used to convert the bit information provided by the

ADE7912/ADE7913 into degrees Celsius has a default value of

8.72101 × 10−5°C/LSB. The temperature measurement accuracy

is ±5°C.

TEMPOS is the 8-bit signed read-only register in which the

temperature sensor offset is stored. The offset information is

calculated during the manufacturing process, and it is stored

with the opposite sign. For example, if the offset is 5, −5 is

written into the ADE7912/ADE7913. One least significant bit

(LSB) of the TEMPOS register is equivalent to 211 LSBs of the

V2WV register.

Instead of using the default gain value, the gain can be

calibrated as part of the overall meter calibration process.

Measure the temperature, TEMP, of every ADE7912/ADE7913,

read the V2WV register containing the temperature sensor

reading of every ADE7912/ADE7913, and compute the gains as

follows:

Temperature gain

TEMPOS

TEMP

(6)

PROTECTING THE INTEGRITY OF CONFIGURATION

REGISTERS

The configuration registers of the ADE7912/ADE7913 are

either user accessible registers (CONFIG, EMI_CTRL,

SYNC_SNAP, COUNTER0, and COUNTER1) or internal

registers. The internal registers are not user accessible, and they

must remain at their default values. To protect the integrity of

all configuration registers, a write protection mechanism is

available.

By default, the protection is disabled and the user accessible

configuration registers can be written without restriction. When

the protection is enabled, no writes to any configuration register

are allowed. The registers can always be read, without

restriction, independent of the write protection state.

To enable the protection, write 0xCA to the 8-bit lock register

(Address 0xA). To disable the protection, write 0x9C to the 8-

bit lock register. It is recommended that the write protection be

enabled after the CONFIG and EMI_CTRL registers are

initialized. If any user accessible register must be changed, for

example, during the synchronization process of multiple

ADE7912/ADE7913 devices, disable the protection, change the

value of the register, and then reenable the protection.

CRC OF CONFIGURATION REGISTERS

Every output cycle, the ADE7912/ADE7913 compute the CRC

of the CONFIG, EMI_CTRL, and TEMPOS registers, as well as

Bit 2 (IC_PROT) of the STATUS0 register, and Bit 7 of the

STATUS1 register. The CRC algorithm is called CRC-16-

CCITT. The 16-bit result is written in the CTRL_CRC register.

The input registers to the CRC circuit form a 64-bit array that is

introduced bit by bit into an LFSR-based generator, similar to

Figure 28 and Figure 29, with one byte at a time, least significant

byte first. Each byte is then processed with the most significant bit

first.

The formulas that govern the LFSR are as follows:

bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that

form the CRC. Bit b0 is the least significant bit, and Bit b15 is the

most significant bit.

gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating

polynomial defined by the CRC-16-CCITT algorithm in

Equation 1 and Equation 2.

FB(j) = aj − 1 XOR b15(j − 1)

(7)

b0(j) = FB(j) AND g0

(8)

bi(j) = FB(j) AND gi XOR bi− 1(j − 1), i = 1, 2, 3, … , 15 (9)

Equation 7, Equation 8, and Equation 9 must be repeated for

j = 1, 2, … , 64. The value written into the CTRL_CRC register

contains Bit bi(64), i = 0, 1, …, 15. Because each ADE7912/

ADE7913 has a particular TEMPOS register value, each ADE7912/

ADE7913 has a different CTRL_CRC register default value.

ADE7912/ADE7913 STATUS

The bits in the STATUS0 and STATUS1 registers of the

ADE7912/ADE7913 characterize the state of the device.

If the value of the CTRL_CRC register changes, Bit 1 (CRC_STAT)

is set to 1 in the STATUS0 register. This bit clears to 0 when the

STATUS0 register is read.

After the configuration registers are protected by writing 0xCA

into the lock register, Bit 2 (IC_PROT) in the STATUS0 register

is set to 1. It clears to 0 when the STATUS0 register is read, and

it is set back to 1 at the next ADC output cycle.

At power-up, or after a hardware or software reset, the

ADE7912/ADE7913 signal the end of the reset period by

clearing Bit 0 (RESET_ON) to 0 in the STATUS0 register.

If the ADC output values of IWV, V1WV, and V2WV are not

read during an output cycle, Bit 3 (ADC_NA) in the STATUS1

read.

The STATUS0 and STATUS1 registers can be read by executing

an SPI register read. STATUS0 can also be read as part of the

SPI burst mode read operation. See the SPI Read Operation and

the SPI Read Operation in Burst Mode sections for more

information.

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