ADE7912 datasheet(30/44 Pages) AD

30 / 44 page

ADE7912/ADE7913

Data Sheet

Rev. 0 | Page 30 of 44

When the DREADY active low pulses are generated, execute the

following steps immediately after the output registers (IWV,

V1WV, V2WV, ADC_CRC, STATUS0, and CNT_SNAPSHOT)

are read:

1. ADC Cycle 0. Disable the protection of the configuration

registers by setting the lock register to 0x9C (see the

Protecting the Integrity of Configuration Registers

section).

Set the 8-bit register SYNC_SNAP to 0x02 using a write

broadcast command. The CA, CB, and CC values of the three

counters are latched and stored in the CNT_SNAPSHOT

2. ADC Cycle 1. The ADE7912/ADE7913 counters (CA, CB,

and CC) latched at Cycle 0 are read in burst mode from the

CNT_SNAPSHOT register together with the IWV, V1WV,

V2WV, ADC_CRC, and STATUS0 registers.

3. ADC Cycle 2. Because CA > CC, the following equation can

be written:

where

is the new value that must be determined.

The new initial counter value,

−

, is

written into the Phase A ADE7912/ADE7913 (labeled

ADE7912A/ADE7913A in Figure 44) in two consecutive

8-bit writes to the COUNTER0 and COUNTER1 registers.

The Phase A ADE7912/ADE7913 device is in synchroniza-

tion with the Phase C ADE7912/ADE7913 starting with

ADC Cycle 4.

Because CB < CC, the following equation can be written:

where

is the new value that must be determined.

The new initial counter value,

−

, is written

into the Phase B ADE7912/ADE7913 in two consecutive 8-

bit writes to the COUNTER0 and COUNTER1 registers.

Phase B ADE7912/ADE7913 is in synchronization with the

Phase C ADE7912/ADE7913 starting with ADC Cycle 4.

As demonstrated, if the latched value of the counter on the

reference Phase X is CX and the initial value of the counter

is C0 (see Table 1 ), the new value of the counter on

Phase Y that is required to bring Phase Y in

synchronization to Phase X is as follows:

If CY > CX, then

−

(10)

If CY ≤ CX, then

−

(11)

4. ADC Cycle 3. The Phase A and Phase B ADE7912/ADE7913

counters start counting down based on the COUNTER1

and COUNTER0 values written during ADC Cycle 2.

5. ADC Cycle 4. All ADE7912/ADE7913 devices generate

ADC outputs synchronously. To verify this, as a good

programming practice, read the counters again so that the

SYNC_SNAP = 0x02 command is executed one more time.

6. ADC Cycle 5. The ADE7912/ADE7913 counters (CA, CB,

and CC), latched after the SYNC_SNAP = 0x02 command,

are stored in the CNT_SNAPSHOT register and are read in

burst mode. They show the same value, ±1 LSB, which

means ±1 CLKIN cycle (±244 ns for CLKIN = 4.096 MHz).

CC = CA ± 1 = CB ± 1

7. Reenable protection of the configuration registers by

setting the lock register to 0xCA (see the Protecting the

Integrity of Configuration Registers section).

The ±1 LSB error may appear because CLKIN, the internal

clock of the ADE7912/ADE7913, is asynchronous to the serial

port clock generated by the microcontroller and is used to write

the COUNTER1 and COUNTER0 values during ADC Cycle 2.

The EMI reduction scheme managed by the EMI_CTRL regis-

ter (see the DC-to-DC Converter section for details) requires

that the ADE7912/ADE7913 devices of the meter system

provide coherent samples. This EMI reduction scheme ensures

that one ADE7912/ADE7913 device does not generate the

PWM signals required to manage the dc-to-dc converter at the

same moment as another ADE7912/ADE7913. The ±1 LSB

error in the counter synchronization means that at least two

ADE7912/ ADE7913 devices generate PWM signals

simultaneously for one CLKIN cycle and the EMI reduction

scheme may be affected. Although there are no guarantees, both

synchronization procedures outlined in this section can be

repeated until CC = CA = CB.

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