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A3952SW 数据表(PDF) 4 Page - Allegro MicroSystems |
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A3952SW 数据表(HTML) 4 Page - Allegro MicroSystems |
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4 / 16 page ![]() 3952 FULL-BRIDGE PWM MOTOR DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Control Logic Logic Supply Voltage Range V CC Operating 4.5 5.0 5.5 V Logic Input Voltage V IN(1) 2.0 –– V V IN(0) –– 0.8 V Logic Input Current I IN(1) V IN = 2.0 V – <1.0 20 µA I IN(0) V IN = 0.8 V – <-2.0 -200 µA Reference Voltage Range V REF Operating 0 – 15 V Reference Input Current I REF V REF = 2.0 V 25 40 55 µA Reference Voltage Divider Ratio – V REF = 15 V 9.5 10.0 10.5 – Comparator Input Offset Voltage V IO V REF = 0 V – ±1.0 ±10 mV PWM RC Fixed OFF Time t off C T = 1000 pF, RT = 20 kΩ 18 20 22 µs PWM Minimum ON Time t on(min) C T = 820 pF, RT ≥ 12 kΩ – 1.7 3.0 µs C T = 1200 pF, RT ≥ 12 kΩ – 2.5 3.8 µs Propagation Delay Time t pd I OUT = ±2.0 A, 50% EIN to 90% EOUT Transition: ENABLE ON to Source ON – 2.9 – µs ENABLE OFF to Source OFF – 0.7 – µs ENABLE ON to Sink ON – 2.4 – µs ENABLE OFF to Sink OFF – 0.7 – µs PHASE Change to Source ON – 2.9 – µs PHASE Change to Source OFF – 0.7 – µs PHASE Change to Sink ON – 2.4 – µs PHASE Change to Sink OFF – 0.7 – µs t pd(pwm) Comparator Trip to Sink OFF – 0.8 1.5 µs Thermal Shutdown Temperature T J – 165 – °C Thermal Shutdown Hysteresis ∆T J – 15 – °C UVLO Disable Threshold V CC(UVLO) 3.15 3.50 3.85 V UVLO Hysteresis ∆V CC(UVLO) 300 400 500 mV Logic Supply Current I CC(ON) V ENABLE = 0.8 V, VBRAKE = 2.0 V – 20 30 mA (No Load) I CC(OFF) V ENABLE = 2.0 V, VMODE = 0.8 V – 12 18 mA I CC(BRAKE) V BRAKE = 0.8 V – 26 40 mA I CC(SLEEP) V ENABLE = VMODE = VBRAKE = 2.0 V – 3.0 5.0 mA NOTES: 1. Typical Data is for design information only. 2. Each driver is tested separately. 3. Negative current is defined as coming out of (sourcing) the specified device terminal. Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units |
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