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GAL22V10D-25LS 数据表(PDF) 14 Page - Lattice Semiconductor |
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GAL22V10D-25LS 数据表(HTML) 14 Page - Lattice Semiconductor |
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14 / 23 page ![]() Specifications GAL22V10 12 GAL22V10D-4 Output Load Conditions (see figure below) Test Condition R1 CL A50Ω 50pF B Z to Active High at 1.9V 50Ω 50pF Z to Active Low at 1.0V 50Ω 50pF C Active High to Z at 1.9V 50Ω 50pF Active Low to Z at 1.0V 50Ω 50pF Input Pulse Levels GND to 3.0V Input Rise and D-4/-5/-7 1.5ns 10% – 90% Fall Times D-10/-15/-20/-25 2.0ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. TEST POINT C * L FROM OUTPUT (O/Q) UNDER TEST +5V *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R2 R1 Output Load Conditions (except D-4) (see figure below) Test Condition R1 R2 CL A 300Ω 390Ω 50pF B Active High ∞ 390Ω 50pF Active Low 300Ω 390Ω 50pF C Active High ∞ 390Ω 5pF Active Low 300Ω 390Ω 5pF TEST POINT Z0 = 50Ω, CL* FROM OUTPUT (O/Q) UNDER TEST +1.45V R1 Switching Test Conditions |
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