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ADN8831ACPZ-R2 数据表(PDF) 4 Page - Analog Devices

部件名 ADN8831ACPZ-R2
功能描述  Thermoelectric Cooler (TEC) Controller
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADN8831ACPZ-R2 数据表(HTML) 4 Page - Analog Devices

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ADN8831
Data Sheet
Rev. A | Page 4 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 3.0 V to 5.0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter1
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PWM OUTPUT DRIVER
Output Transition Time
t
R, tF
C
L = 3300 pF
20
ns
Nonoverlapping Clock Delay
40
80
ns
Output Resistance
R
O (SNGATE, SPGATE)
I
L = 10 mA, VDD = 3.0 V
6
Ω
Output Voltage Swing2
SFB
V
LIM = VREF
0
V
DD
V
LINEAR OUTPUT AMPLIFIER
Output Resistance
R
O, LNGATE
I
OUT = 2 mA, VDD = 3.0 V
200
Ω
R
O, LPGATE
I
OUT = 2 mA, VDD = 3.0 V
100
Ω
Output Voltage Swing2
LFB
0
V
DD
V
POWER SUPPLY
Power Supply Voltage
V
DD
3.0
5.5
V
Supply Current
I
SY
PWM not switching
8
12
mA
−40°C ≤ T
A ≤ +85°C
15
mA
Shutdown Current
I
SD
SYNCI/SD = 0 V
8
µA
Soft Start Charging Current
I
SS
V
SS = 0 V
8
µA
Undervoltage Lockout3
UVLO
Low to high threshold
2.2
2.6
V
Standby Current
I
SB
SYNCI/SD = VDD, SS/SB = 0 V
2
mA
Standby Threshold
V
SB
SYNCI/SD = VDD
150
200
mV
ERROR/COMPENSATION AMPLIFIERS
Input Offset Voltage
V
OS1
V
CM1 = 1.5 V, VIN1P − VIN1M
10
100
μV
V
OS2
V
CM2 = 1.5 V, VIN2P − VIN2M
10
100
μV
Input Voltage Range
V
CM1, VCM2
0
V
DD
V
Common-Mode Rejection Ratio
CMRR
1, CMRR2
V
CM1, VCM2 = 0.2 V to VDD − 0.2 V
120
dB
Output Voltage High
V
OH1, VOH2
V
DD − 0.03
V
Output Voltage Low
V
OL1, VOL2
25
mV
Power Supply Rejection Ratio
PSRR
1, PSRR2
3.0 V ≤ V
DD ≤ 5.0 V
110
dB
Output Current
I
OUT1, IOUT2
Sourcing and sinking
5
mA
Gain Bandwidth Product
GBW
1, GBW2
V
OUT = 0.5 V to (VDD − 1 V)
2
MHz
OSCILLATOR
Sync Range
f
CLK
SYNCI/SD connected to external
clock
300
1000
kHz
Oscillator Frequency
f
CLK
COMPOSC = V
DD, RFREQ = 118 kΩ,
SYNCI/SD = VDD, VDD = 5.0V
800
1000
1250
kHz
Nominal Free-Run Oscillation
Frequency
f
CLK-NOMINAL
COMPOSC = V
DD, SYNCI/SD = VDD
200
1000
kHz
Phase Adjustment Range2
Φ
CLK
V
PHASE = 0.13 V, fSYNCI/SD = 1 MHz
50
Degrees
V
PHASE = 2.3 V, fSYNCI/SD = 1 MHz
330
Degrees
Phase Adjustment Default
Φ
CLK
PHASE = open
180
Degrees
REFERENCE VOLTAGE
Reference Voltage
V
REF
I
REF = 2 mA
2.35
V
I
REF = 0 mA
2.37
2.47
2.57
V



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