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A8905CLB 数据表(PDF) 4 Page - Allegro MicroSystems

部件名 A8905CLB
功能描述  3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
PDF  12 Pages
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制造商  ALLEGRO [Allegro MicroSystems]
网页  http://www.allegromicro.com
标志 ALLEGRO - Allegro MicroSystems

A8905CLB 数据表(HTML) 4 Page - Allegro MicroSystems

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8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
CWD Threshold Voltage
VTL
0.80
0.85
0.95
V
VTH
2.4
2.75
3.0
V
Max. FLL Oscillator Frequency
fOSC
VDD = 5.1 V, TA = 25°C20
MHz
VDD = 4.5 V, TA = 70°C—
10
MHz
IOUT(MAX) Accuracy
IOUT = 1 A
±20
%
BRAKE Threshold
VBRK
1.4
1.7
2.0
V
Transconductance Gain
gm
0.26
0.35
0.50
A/V
Centertap Resistors
RCT
5.0
10
13
k
Back-EMF Hysteresis
VBEMF - VCTAP at
152540
mV
FCOM Transition
-15
-25
-40
mV
ELECTRICAL CHARACTERISTICS continued
A. Minimum CHIP SELECT setup time before CLOCK rising edge ...... 100 ns
B. Minimum CHIP SELECT hold time after CLOCK rising edge ........... 150 ns
C. Minimum DATA setup time before CLOCK rising edge .................... 150 ns
D. Minimum DATA hold time after CLOCK rising edge ........................ 150 ns
E. Minimum CLOCK low time before CHIP SELECT .............................. 50 ns
F. Maximum CLOCK frequency ........................................................... 3.3 MHz
DATA
CLOCK
Dwg. WP-019
A
C
B
D
C
D
CHIP SELECT
E
SERIAL PORT TIMING CONDITIONS



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