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MP8760GL 数据表(PDF) 13 Page - Monolithic Power Systems |
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MP8760GL 数据表(HTML) 13 Page - Monolithic Power Systems |
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13 / 24 page ![]() MP8760 — 6A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER MP8760 Rev. 1.1 www.MonolithicPower.com 13 11/4/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. switching frequency stays fairly constant over the output current range. Switching Frequency Selecting the switching frequency requires trading off between efficiency and component size. Low-frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductor and capacitor values to minimize the output voltage ripple. For the MP8760, set the ON time using the FREQ pin, thus setting the frequency for steady- state operation at CCM. The MP8760 uses adaptive constant-on-time (COT) control, though the IC lacks a dedicated oscillator. Connect the FREQ pin to the IN pin through the resistor (RFREQ) so that the input voltage is feed-forwarded to the one-shot on-time timer. When operating in steady-state in CCM, the duty ratio stays at VOUT/VIN so the switching frequency is fairly constant over the input voltage range. Set switching frequency as follows: ) ns ( ) V ( V ) V ( V . ) V ( V ) k ( R . ) kHz ( f DELAY OUT IN IN FREQ SW τ + × − Ω × = 4 0 3 5 106 (3) Where τDELAY is the comparator delay (~40ns). Typically, the MP8760 is set between 200kHz and 1MHz. It is optimized to operate efficiently at high switching frequencies, which allow for physically smaller LC filter components to reduce the PCB footprint. Jitter and FB Ramp Slope Figure 4 and Figure 5 show jitter occurring in both PWM mode and skip mode. When there is noise on the VFB descending slope, the HS-FET ON time deviates from its intended appoint, introducing jitter that influences the system’s stability. The VFB ripple’s slope steepness dominates the noise immunity though its magnitude has no direct effect. Figure 4: PWM-Mode Jitter Figure 5: Skip-Mode Jitter Ramp with a Large ESR Capacitor Using POSCAPs or other large-ESR capacitors as the output capacitor results in the ESR ripple dominating the output ripple. The ESR also significantly influences the VFB slope. Figure 6 shows the simplified equivalent circuit in PWM mode with the HS-FET OFF and without an external ramp circuit. R1 R2 ESR POSCAP SW VOUT L FB Figure 6: Simplified PWM-Mode Circuit without External Ramp Compensation To realize the stability without an external ramp, select the ESR value as follows: OUT ON SW ESR C . R 2 7 0 τ + π × τ ≥ (4) Where τSW is the switching period. |
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