AX1000 datasheet(97/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

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Sample Implementations

Frequency Synthesis

Figure 2-53 illustrates an example where the PLL is used to multiply a 155.5 MHz external clock up to

622 MHz. Note that the same PLL schematic could use an external 350 MHz clock, which is divided

down to 155 MHz by the FPGA internal logic.

Figure 2-54 illustrates the PLL using both dividers to synthesize a 133 MHz output clock from a 155 MHz

input reference clock. The input frequency of 155 MHz is multiplied by 6 and divided by 7, giving a CLK1

output frequency of 132.86 MHz. When dividers are used, a given ratio can be generated in multiple

ways, allowing the user to stay within the operating frequency ranges of the PLL.

Adjustable Clock Delay

Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable

delay lines. In this case, the output clock is delayed relative to the reference clock. Delaying the

reference clock relative to the output clock is accomplished by using the delay line in the feedback path.

Figure 2-53 • Using the PLL 155.5 MHz In, 622 MHz Out

Delay Line

PLL

Delay Line

RefCLK

CLK1

Power-Down

Lock

CLK2

FBMuxSel

DividerI

DelayLine

DividerJ

LowFreq

Osc

155.5 MHz

622 MHz

/i Delay

Match

/j Delay

Match

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