MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER

MP28115 Rev. 0.92

www.MonolithicPower.com

7

8/23/2010

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FUNCTIONAL DESCRIPTION

PWM Control

The MP28115 is a constant frequency peak-

current-mode control PWM switching regulator.

Refer to the functional block diagram, The high

side N-Channel DMOS power switch is turns on

at the beginning of each clock cycle. The current

in the inductor increases until the PWM current

comparator trips to turn off the high side DMOS

switch. The peak inductor current at which the

current comparator shuts off the high side power

switch is controlled by the COMP voltage at the

output

of

feedback

error

amplifier.

The

transconductance from the COMP voltage to the

output current is set at 11.25A/V.

This current-mode control greatly simplifies the

feedback compensation design by approximating

the switching converter as a single-pole system.

Only Type II compensation network is needed,

which is integrated into the MP28115. The loop

bandwidth is adjusted by changing the upper

resistor value of the resistor divider at the FB pin.

The internal compensation in the MP28115

simplifies the compensation design, minimizes

external component counts, and keeps the

flexibility of external compensation for optimal

stability and transient response.

Enable and Frequency Synchronization

(EN/SYNC PIN)

This is a dual function input pin. Forcing this pin

below 0.4V for longer than 4μs shuts down the

part; forcing this pin above 1.6V for longer than

4µs turns on the part. Applying a 1MHz to 2MHz

clock signal to this pin also synchronizes the

internal oscillator frequency to the external clock.

When the external clock is used, the part turns

on after detecting the first few clocks regardless

of duty cycles. If any ON or OFF period of the

clock is longer than 4µs, the signal will be

intercepted as an enable input and disables the

synchronization.

Soft-Start and Output Pre-Bias Startup

When the soft-start period starts, an internal

current source begins charging an internal soft-

start capacitor. During soft-start the voltage on

the soft-start capacitor is connected to the non-

inverting input of the error amplifier. The soft-start

period lasts until the voltage on the soft-start

capacitor exceeds the reference voltage of 0.8V.

At this point the reference voltage takes over at

the non-inverting error amplifier input. The soft-

start time is internally set at 120µs. If the output

of the MP28115 is pre-biased to a certain voltage

during startup, the IC will disable the switching of

both high-side and low-side switches until the

voltage on the internal soft-start capacitor

exceeds the sensed output voltage at the FB pin.

Over current Protection

The MP28115 offers cycle-to-cycle current

limiting for both high-side and low-side switches.

The high-side current limit is relatively constant

regardless of duty cycles. When the output is

shorted to ground, causing the output voltage to

drop below 70% of its nominal output, the IC is

shut down momentarily and begins discharging

the soft start capacitor. It will restart with a full

soft-start when the soft- start capacitor is fully

discharged. This hiccup process is repeated until

the fault is removed.

Power Good Output (POK PIN)

The MP28115 includes an open-drain Power

Good output that indicates whether the regulator

output is within ±10% of its nominal output. When

the output voltage moves outside this range, the

POK output is pulled to ground. There is a 30µs

deglitch time when the POK output change its

state.

Bootstrap (BST PIN)

The gatedriver voltage for the high-side N-

channel DMOS power switch is supplied by a

bootstrap capacitor connected between the BS

and SW pins. When the low-side switch is on, the

capacitor is charged through an internal boost

diode. When the high-side switch is off and the

low-side switch turns on, the voltage on the

bootstrap capacitor is boosted above the input

voltage and the internal bootstrap diode prevents

the capacitor from discharging.

.