REV. B

–18–

AD7722

Varying the Master Clock

Although the AD7722 is specified with a master clock of 12.5 MHz,

the AD7722 operates with clock frequencies up to 15 MHz and

as low as 300 kHz. The input sample rate, output word rate, and

frequency response of the digital filter are directly proportional

to the master clock frequency. For example, reducing the clock

frequency to 5 MHz leads to an analog input sample rate of

10 MHz, an output word rate of 78.125 kSPS, a pass-band

frequency of 36.25 kHz, a cutoff frequency of 38.77 kHz, and a

stop-band frequency of 41.875 kHz.

SYSTEM SYNCHRONIZATION AND CONTROL

The AD7722 digital filter contains a sequencer block that

controls the digital interface and all the control logic needed to

operate the digital filter. A 14-bit cycle counter keeps track of

where the filters are in their overall operating cycle and decodes

the digital interface signals to the AD7722. The cycle counter

has a number of important transition points. In particular, the

bottom six bits control the convolution counter that decimates

by 64 to the update rate of the output data register. The counter’s

top bit is used to provide ample time (8192 CLKIN cycles) to

allow the modulator and digital filter to settle as the AD7722

sequences through its autocalibration process. The counter

increments on the rising edge of the signal at the CLKIN pin and

all of the digital I/O signals are synchronous with this clock. The

upper bit of this counter also controls when DVAL or

DRDY

indicates that valid data is available in the output data register

after a SYNC, RESET, CAL, or initial FSI. During normal

operation, the delay of 128 conversions (8192 CLKIN cycles)

should not be confused with the actual settling time (5376

CLKIN cycles) and group delay (2688 CLKIN cycles) of the

digital filter.

SYNC Input

The SYNC input provides a synchronization function for use in

parallel or serial mode. SYNC allows the user to start gathering

samples of the analog input from a known point in time. This

allows a system using multiple AD7722s, operated from a common

master clock, to be synchronized so that each ADC updates its

output register simultaneously. The SYNC input resets the digital

filter without affecting the contents of the calibration registers.

In a system using multiple AD7722s, a common signal to their

sync input will synchronize their operation. On the rising edge

of SYNC, the digital filter sequencer counter is reset to zero.

The filter is held in a reset state until a rising edge on CLKIN

senses SYNC low. A SYNC pulse, one CLKIN cycle long, can

be applied synchronous to the falling edge of CLKIN. This way,

on the next rising edge of CLKIN, SYNC is sensed low, the

filter is taken out of its reset state, and multiple parts start to

gather input samples.

In serial mode, DVAL remains low for 8192 CLKIN cycles to

allow the modulator and digital filter to settle. In parallel mode,

DRDY remains high for an additional 64 CLKIN cycles when

valid data is loaded into the output register. After a SYNC, conver-

sion data is not valid until the digital filter settles (see Figure 7).

DVAL

The DVAL pin, when used in the serial mode, indicates if invalid

data may be present at the ADC output. There are four events that

can cause DVAL to be deasserted, and they have different impli-

cations for how long the results should be considered invalid.

DVAL is set low if there is an overflow condition in the first stage

of the digital filter. The overflow can result from an analog input

signal nearly twice the allowable maximum input span. When an

overflow condition is detected, DVAL is set low for 64 CLKIN

cycles (one output period) and the output data is clipped to

either positive or negative full scale depending on the sign of the

overflow. After the next convolution is completed (64 CLKIN

cycles), if the overflow condition does not exist, DVAL goes

high to indicate that a valid output is available. Otherwise, DVAL

will remain low until the overflow condition is eliminated.

The second stage digital filter can overflow as a result of overflow

from the first stage. The overflow condition is detected when

the second stage filter calculates a conversion result that exceeds

either plus or minus full scale (i.e., below –32,768 or above

32,767 in bipolar mode). When the overflow is detected, DVAL

is set low and the output register is updated with either positive

or negative full scale, depending on the sign of the overload.

After the next convolution is completed, DVAL returns high

if the next conversion result is within the full-scale range.

As with all high order

Σ-∆ modulators, large overloads on the

analog input can cause the modulator to go unstable. The

modulator is designed to be stable with input signals as high as

twice full scale within the input bandwidth. Out-of-band signals

as high as the full-scale range will not cause instability. When

instability is detected by internal circuits, DVAL is set low and

the output is clipped to either positive or negative full scale

depending on the polarity of the overload. The modulator is

reset to a stable state, and the digital filter sequencer counter is

reset. DVAL is set low for a minimum of 8192 CLKIN cycles

while the modulator settles out, and the digital filter accumu-

lates new samples. DVAL returns high to indicate that valid

data is available from the serial output register 8192 CLKIN

cycles after the overload condition is removed.

Lastly, DVAL also indicates when valid data is available at the

serial interface after initial power-up or upon completion of a

CAL, RESET, or SYNC sequence.

Reset Input

The AD7722 RESET input controls the digital filter the same

as the SYNC input described previously. Additionally, it resets

the modulator by shorting its integrator capacitors and clears

the on-chip calibration registers so that the conversion results

are not corrected for offset or gain error.

Power-On Reset

A power-on reset function is provided to reset the AD7722

internal logic after initial power-up. On power-up, the offset and

gain calibration registers are cleared.