REV. B

AD7722

–19–

Offset and Gain Calibration

A calibration of offset and gain errors can be performed in both

serial and parallel modes by initiating a calibration cycle. During

this cycle, offset and gain registers in the filter are loaded with

values representing the dc offset of the analog modulator and a

modulator gain correction factor. The correction factors are

determined by an on-chip microcontroller measuring the conver-

sion results for three different input conditions: minus full scale

(–FS), plus full scale (+FS), and midscale. In normal operation,

the offset register is subtracted from the digital filter output and

the result is multiplied by the gain correction factor to obtain an

offset and gain corrected final result.

The calibration cycle is controlled by internal logic, and the user

need only initiate the cycle. A calibration is initiated when the

rising edge of CLKIN senses a high level on the CAL input.

There is an uncertainty of up to 64 CLKIN cycles before the

calibration cycle actually begins because the current conversion

must complete before calibration commences. The calibration

values loaded into the registers only apply for the particular

analog input mode (bipolar/unipolar) selected when initiating

the calibration cycle. On changing to a different analog input

mode, a new calibration must be performed.

During the calibration cycle, in unipolar mode, the offset of the

analog modulator is evaluated; the differential inputs to the

modulator are shorted internally to AGND. Once calibration

begins, DVAL goes low and

DRDY goes high, indicating there

is invalid data in the output register. After 8192 CLKIN cycles,

when the modulator and digital filter settle, the average of eight

output results (512 CLKIN cycles) is calculated and stored in

the offset register. In unipolar mode, this result also represents

minus full scale, required to calculate the gain correction factor.

The gain correction factor can then be determined by internally

modulator is switched to the reference voltage and the negative

input to AGND. Again, when the modulator and digital filter

settle, the average of the eight output results is used to calculate

the gain correction factor. DVAL goes high whenever a calcula-

tion is performed on the average of eight conversion results

(512 CLKIN cycles) and then returns low. See Figure 8.

In bipolar mode, an additional measurement is required since

zero scale is not the same as –FS. Therefore, calibration in

bipolar mode requires an additional (512 + 8192) CLKIN

cycles. Zero scale is similarly determined by shorting both

analog inputs to AGND. Then the inputs are internally

to determine the gain correction factor.

After the calibration registers have been loaded with new values,

the inputs of the modulator are switched back to the input pins.

However, correct data is available at the interface only after the

modulator and filter have settled to the new input values.

Should the part see a rising edge on the SYNC or RESET pin

during a calibration cycle, the calibration cycle is discontinued,

and a synchronization operation or reset will be performed.

The calibration registers are static. They need to be updated

only if unacceptable drifts in analog offsets or gain are expected.

After power-up, a RESET is not mandatory since power-on reset

circuitry clears the offset and gain registers. Care must be taken

to ensure that the CAL pin is held low during power-up. Before

initiating a calibration routine, ensure that the supplies and

reference input have settled, and that the voltage on the analog

input pins is between the supply voltages.

DATA INTERFACING

The AD7722 offers a choice of serial or parallel data interface

options to meet the requirements of a variety of system configu-

rations. In parallel mode, multiple AD7722s can be easily

configured to share a common data bus. Serial mode is ideal

when it is required to minimize the number of data interface

lines connected to a host processor. In either case, careful

attention to the system configuration is required to realize the

high dynamic range available with the AD7722. Consult the

recommendations in the Power Supply Grounding and Layout

section. The following recommendations for parallel interfacing

also apply for the system design in serial mode.

Parallel Interface

When using the AD7722, place a buffer/latch adjacent to the

converter to isolate the converter’s data lines from any noise

that may be on the data bus. Even though the AD7722 has

three-state outputs, use of an isolation latch represents good

design practice. This arrangement will inject a small amount of

digital noise on the AD7722 ground plane; these currents

should be quite small and can be minimized by ensuring that

the converter input/output does not drive a large fanout (they

normally can’t by design). Minimizing the fanout on the

AD7722’s digital port will also keep the converter logic transi-

tions relatively free from ringing and thereby minimize any

potential coupling into the analog port of the converter.

The simplified diagram (Figure 23) shows how the parallel

interface of the AD7722 can be configured to interface with the

system data bus of a microprocessor or a modern microcontroller,

such as the MC68HC16 or 8xC251.

AD7722

ADDR

DECODE

DB0–DB15

DRDY

CS

RD

16

16

74xx16374

OR

74xx16244

OE

D0–D15

RD

INTERRUPT

ADDR

DSP/µC

Figure 23. Parallel Interface Connection

With

CS and RD tied permanently low, the data output bits are

always active. When the

DRDY output goes high for two CLKIN

cycles, the rising edge of

DRDY is used to latch the conversion

data before a new conversion result is loaded into the output

data register. The falling edge of

DRDY then sends an appro-

priate interrupt signal for interface control. Alternatively if buffers

are used instead of latches, the falling edge of

DRDY provides

the necessary interrupt when a new output word is available

from the AD7722.