AM79C970AVCW datasheet(71/219 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C970A

the PCnet-PCI II controller returns ownership for the last

buffer of the first frame.

If an error occurs in the transmission before all of the

bytes of the current buffer have been transferred, trans-

mit status of the current buffer will be immediately up-

dated. If the buffer does not contain the end of packet,

the PCnet-PCI II controller will skip over the rest of the

frame which experienced the error. This is done by re-

turning to the polling microcode where the PCnet-PCI II

controller will clear the OWN bit for all descriptors with

OWN = 1 and STP = 0 and continue in like manner until a

descriptor with OWN = 0 (no more transmit frames in the

ring) or OWN = 1 and STP = 1 (the first buffer of a new

frame) is reached.

At the end of any transmit operation, whether successful

or with errors, immediately following the completion of

the descriptor updates, the PCnet-PCI II controller will

always perform another polling operation. As described

earlier, this polling operation will begin with a check of

the current RDTE, unless the PCnet-PCI II controller al-

ready owns that descriptor. Then the PCnet-PCI II con-

troller will poll the next TDTE. If the transmit descriptor

OWN bit has a ZERO value, the PCnet-PCI II controller

will resume incrementing the poll time counter. If the

transmit descriptor OWN bit has a value of ONE, the

PCnet-PCI II controller will begin filling the FIFO with

transmit data and initiate a transmission. This end-of-

operation poll coupled with the TDTE lookahead opera-

tion allows the PCnet-PCI II controller to avoid inserting

poll time counts between successive transmit frames.

By default, whenever the PCnet-PCI II controller com-

pletes a transmit frame (either with or without error) and

writes the status information to the current descriptor,

then the TINT bit of CSR0 is set to indicate the comple-

tion of a transmission. This causes an interrupt signal if

the IENA bit of CSR0 has been set and the TINTM bit of

CSR3 is cleared. The PCnet-PCI II controller provides

two modes to reduce the number of transmit interrupts.

The interrupt of a successfully transmitted frame can be

suppressed by setting TINTOKD (CSR5, bit 15) to ONE.

Another mode, which is enabled by setting LTINTEN

(CSR5, bit 14) to ONE, allows suppression of interrupts

for successful transmissions for all but the last frame in

a sequence.

Receive Descriptor Table Entry

If the PCnet-PCI II controller does not own both the cur-

rent and the next Receive Descriptor Table Entry

(RDTE) then the PCnet-PCI II controller will continue to

poll according to the polling sequence described above.

If the receive descriptor ring length is one, then there is

no next descriptor to be polled.

If a poll operation has revealed that the current and the

next RDTE belong to the PCnet-PCI II controller then

additional poll accesses are not necessary. Future poll

operations will not include RDTE accesses as long as

the PCnet-PCI II controller retains ownership of the cur-

rent and the next RDTE.

When receive activity is present on the channel, the

PCnet-PCI II controller waits for the complete address

of the message to arrive. It then decides whether to ac-

cept or reject the frame based on all active addressing

schemes. If the frame is accepted the PCnet-PCI II con-

troller checks the current receive buffer status register

CRST (CSR41) to determine the ownership of the

current buffer.

If ownership is lacking, the PCnet-PCI II controller will

immediately perform a final poll of the current RDTE. If

ownership is still denied, the PCnet-PCI II controller has

no buffer in which to store the incoming message. The

MISS bit will be set in CSR0 and the Missed Frame

Counter (CSR112) will be incremented. An interrupt will

be generated if IENA (CSR0, bit 6) is set to ONE and

MISSM (CSR3, bit 12) is cleared to ZERO. Another

poll of the current RDTE will not occur until the frame

has finished.

If the PCnet-PCI II controller sees that the last poll

(either a normal poll, or the final effort described in the

above paragraph) of the current RDTE shows valid own-

ership, it proceeds to a poll of the next RDTE. Following

this poll, and regardless of the outcome of this poll,

transfers of receive data from the FIFO may begin.

Regardless of ownership of the second receive

descriptor, the PCnet-PCI II controller will continue to

perform receive data DMA transfers to the first buffer. If

the frame length exceeds the length of the first buffer,

and the PCnet-PCI II controller does not own the second

buffer, ownership of the current descriptor will be

passed back to the system by writing a ZERO to

the OWN bit of RMD1 and status will be written

indicating buffer (BUFF = 1) and possibly overflow

(OFLO = 1) errors.

If the frame length exceeds the length of the first (cur-

rent) buffer, and the PCnet-PCI II controller does own

the second (next) buffer, ownership will be passed back

to the system by writing a ZERO to the OWN bit of

RMD1 when the first buffer is full. The OWN bit is the

only bit modified in the descriptor. Receive data

transfers to the second buffer may occur before the

PCnet-PCI II controller proceeds to look ahead to the

ownership of the third buffer. Such action will depend

upon the state of the FIFO when the OWN bit has been

updated in the first descriptor. In any case, lookahead

will be performed to the third buffer and the information

gathered will be stored in the chip, regardless of the

state of the ownership bit.

This activity continues until the PCnet-PCI II controller

recognizes the completion of the frame (the last byte of

this receive message has been removed from the

FIFO). The PCnet-PCI II controller will subsequently

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