AM79C970AVCW datasheet(94/219 Pages) AMD

94 / 219 page

AMD

P R E L I M I N A R Y

Am79C970A

controller assumes that an external pulldown device is

holding the EESK/

LED1/SFBD pin low indicating that

there is no EEPROM in the system. Note that if the de-

signer creates a system that contains an LED circuit on

the EESK/

LED1/SFBD pin but has no EEPROM pre-

sent, then the EEPROM auto-detection function will in-

correctly conclude that an EEPROM is present in the

system. However, this will not pose a problem for the

PCnet-PCI II controller, since the checksum verification

will fail.

Direct Access to the Microwire Interface

The user may directly access the Microwire port through

the EEPROM register, BCR19. This register contains

bits that can be used to control the Microwire interface

pins. By performing an appropriate sequence of ac-

cesses to BCR19, the user can effectively write to and

read from the EEPROM. This feature may be used by a

system configuration utility to program hardware con-

figuration information into the EEPROM.

EEPROM-programmable Registers

The following registers contain configuration informa-

tion that will be programmed automatically during the

EEPROM read operation:

s I/O offsets 0h–Fh

Address PROM locations

s BCR2

Miscellaneous Configuration

s BCR4

Link Status LED register

s BCR5

LED1 Status register

s BCR6

LED2 Status register

s BCR7

LED3 Status register

s BCR9

Full-Duplex Control register

s BCR18

Burst and Bus Control

s BCR22

PCI Latency register

If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)

are cleared to ZERO, then the EEPROM read has

experienced a failure and the contents of the EEPROM

programmable BCR register will be set to default

H_RESET values. The content of the Address PROM

locations, however, will not be cleared.

Note that accesses to the Address PROM I/O locations

do not directly access the Address EEPROM itself. In-

stead, these accesses are routed to a set of shadow reg-

isters on board the PCnet-PCI II controller that are

loaded with a copy of the EEPROM contents during the

automatic read operation that immediately follows the

H_RESET operation.

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