AM79C972BVCW datasheet(71/130 Pages) AMD

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Am79C972

bit is 0. After the RESET bit is cleared, then the normal

flow continues.

External Address Detection Interface

The EADI is provided to allow external address filtering

and to provide a Receive Frame Tag word for propri-

etary routing information. It is selected by setting the

EADISEL bit in BCR2 to 1. This feature is typically uti-

lized by terminal servers, bridges and/or router prod-

ucts. The EADI interface can be used in conjunction

with external logic to capture the packet destination ad-

dress from the serial bit stream as it arrives at the

Am79C972 controller, to compare the captured ad-

dress with a table of stored addresses or identifiers,

and then to determine whether or not the Am79C972

controller should accept the packet.

External Address Detection Interface: GPSI Port

The EADI interface outputs are delivered directly from

the NRZ decoded data and clock recovered by the ex-

ternal PHY. This allows the external address detection

to be performed in parallel with frame reception and ad-

dress comparison in the MAC Station Address Detec-

tion (SAD) block of the Am79C972 controller.

SRDCLK is provided to allow clocking of the receive bit

stream into the external address detection logic. Once

a received frame commences and data and clock are

available, the EADI logic will monitor the alternating

(“1,0”) preamble pattern until the two 1s of the Start

Frame Delimiter (SFD, 10101011 bit pattern) are de-

tected, at which point the SFBD output will be driven

HIGH.

The SFBD signal will initially be LOW. The assertion of

SFBD is a signal to the external address detection logic

that the SFD has been detected and that subsequent

SRDCLK cycles will deliver packet data to the external

logic. Therefore, when SFBD is asserted, the external

address matching logic should begin de-serialization of

the SRD data and send the resulting destination ad-

dress to a Content Addressable Memory (CAM) or

other address detection device. In order to reduce the

amount of logic external to the Am79C972 controller for

multiple address decoding systems, the SFBD signal

will toggle at each new byte boundary within the

packet, subsequent to the SFD. This eliminates the

need for externally supplying byte framing logic.

SRD is the decoded NRZ data from the network. This

signal can be used for external address detection.

The EAR pin should be driven LOW by the external ad-

dress comparison logic to reject a frame.

If an address match is detected by comparison with ei-

ther the Physical Address or Logical Address Filter reg-

isters contained within the Am79C972 controller or the

frame is of the type 'Broadcast', then the frame will be

accepted regardless of the condition of EAR. When the

EADISEL bit of BCR2 is set to 1 and the Am79C972

controller is programmed to promiscuous mode

(PROM bit of the Mode Register is set to 1), then all in-

coming frames will be accepted, regardless of any ac-

tivity on the EAR pin.

Internal address match is disabled when PROM

(CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the

Logical Address Filter registers (CSR8 to CSR11) are

programmed to all zeros.

When the EADISEL bit of BCR2 is set to 1 and internal

address match is disabled, then all incoming frames

will be accepted by the Am79C972 controller, unless

the EAR pin becomes active during the first 64 bytes of

the frame (excluding preamble and SFD). This allows

external address lookup logic approximately 58 byte

times after the last destination address bit is available

to generate the EAR signal, assuming that the

Am79C972 controller is not configured to accept runt

packets. The EADI logic only samples EAR from 2 bit

times after SFD until 512 bit times (64 bytes) after SFD.

The frame will be accepted if EAR has not been as-

serted during this window. In order for the EAR pin to

be functional in full-duplex mode, FDRPAD bit (BCR9,

bit 2) needs to be set. If Runt Packet Accept (CSR124,

bit 3) is enabled, then the EAR signal must be gener-

ated prior to the 8 bytes received, if frame rejection is

to be guaranteed. Runt packet sizes could be as short

as 12 byte times (assuming 6 bytes for source address,

2 bytes for length, no data, 4 bytes for FCS) after the

last bit of the destination address is available. EAR

must have a pulse width of at least 110 ns.

The EADI outputs continue to provide data throughout

the reception of a frame. This allows the external logic

to capture frame header information to determine pro-

tocol type, internetworking information, and other use-

ful data.

The EADI interface will operate as long as the STRT bit

in CSR0 is set, even if the receiver and/or transmitter

are disabled by software (DTX and DRX bits in CSR15

are set). This configuration is useful as a semi-power-

down mode in that the Am79C972 controller will not

perform any power-consuming DMA operations. How-

ever, external circuitry can still respond to control

frames on the network to facilitate remote node control.

Table 8 summarizes the operation of the EADI inter-

face.

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