AM79C972BVCW datasheet(83/130 Pages) AMD

83 / 130 page

Am79C972

Table 10.

EEPROM Map

The LED pins can be configured to operate in either

open-drain mode (active low) or in totem-pole mode

(active high). The output can be stretched to allow the

human eye to recognize even short events that last only

several microseconds. After H_RESET, the four LED

outputs are configured as shown in Table 11.

Word

Address

Byte

Address

Most Significant Byte

Byte

Address

Least Significant Byte

00h*

01h

2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3)

station physical address for this node.

00h

First byte of the ISO 8802-3 (IEEE/ANSI

802.3) station physical address for this

node, where “first byte” refers to the first

byte to appear on the 802.3 medium.

01h

03h

4th byte of the node address

02h

3rd byte of the node address

02h

05h

6th byte of the node address

04h

5th byte of the node address

03h

07h

CSR116[15:8] (OnNow Misc. Config.)

06h

CSR116[7:0] (OnNow Misc. Config.)

04h

09h

Hardware ID; must be 11h if compatibility to

AMD drivers is desired

08h

Reserved location: must be 00h

05h

0Bh

User programmable space

0Ah

User programmable space

06h

0Dh

MSB of two-byte checksum, which is the sum

of bytes 00h-0Bh and bytes 0Eh and 0Fh

0Ch

LSB of two-byte checksum, which is the

sum of bytes 00h-0Bh and bytes 0Eh and

0Fh

07h

0Fh

Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired

0Eh

Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired

08h

11h

BCR2[15:8] (Miscellaneous Configuration)

10h

BCR2[7:0] (Miscellaneous Configuration)

09h

13h

BCR4[15:8] (Link Status LED)

12h

BCR4[7:0] (Link Status LED)

0Ah

15h

BCR5[15:8] (LED1 Status)

14h

BCR5[7:0] (LED1 Status)

0Bh

17h

BCR6[15:8] (LED2 Status)

16h

BCR6[7:0] (LED2 Status)

0Ch

19h

BCR7[15:8] (LED3 Status)

18h

BCR7[7:0] (LED3 Status)

0Dh

1Bh

BCR9[15:8] (Full-Duplex Control)

1Ah

BCR9[7:0] (Full-Duplex Control)

0Eh

1Dh

BCR18[15:8] (Burst and Bus Control)

1Ch

BCR18[7:0] (Burst and Bus Control)

0Fh

1Fh

BCR22[15:8] (PCI Latency)

1Eh

BCR22[7:0] (PCI Latency)

10h

21h

BCR23[15:8] (PCI Subsystem Vendor ID)

20h

BCR23[7:0] (PCI Subsystem Vendor ID)

11h

23h

BCR24[15:8] (PCI Subsystem ID)

22h

BCR24[7:0] (PCI Subsystem ID)

12h

25h

BCR25[15:8] (SRAM Size)

24h

BCR25[7:0] (SRAM Size)

13h

27h

BCR26[15:8] (SRAM Boundary)

26h

BCR26[7:0] (SRAM Boundary)

14h

29h

BCR27[15:8] (SRAM Interface Control)

28h

BCR27[7:0] (SRAM Interface Control)

15h

2Bh

BCR32[15:8] (MII Control and Status)

2Ah

BCR32[7:0] (MII Control and Status)

16h

2Dh

BCR33[15:8] (MII Address)

2Ch

BCR33[7:0] (MII Address)

17h

2Fh

BCR35[15:8] (PCI Vendor ID)

2Eh

BCR35[7:0] (PCI Vendor ID)

18h

31h

BCR36[15:8] (Conf. Space byte 43h alias)

30h

BCR36[7:0] (Conf. Space byte 42h alias)

19h

33h

BCR37[15:8] (DATA_SCALE alias 0)

32h

BCR37[7:0] (Conf. Space byte 47h 0 alias)

1Ah

35h

BCR38[15:8] (DATA_SCALE alias 1)

34h

BCR38[7:0] (Conf. Space. byte 47h 1 alias)

1Bh

75h

BCR39[15:8] (DATA_SCALE alias 2)

36h

BCR39[7:0] (Conf. Space. byte 47h 2 alias)

1Ch

39h

BCR40[15:8] (DATA_SCALE alias 3)

38h

BCR40[7:0] (Conf. Space. byte 47h 3 alias)

1Dh

3Bh

BCR41[15:8] (DATA_SCALE alias 4)

3Ah

BCR41[7:0] (Conf. Space. byte 47h 4 alias)

1Eh

3Dh

BCR42[15:8] (DATA_SCALE alias 0)

3Ch

BCR42[7:0] (Conf. Space. byte 47h 5 alias)

1Fh

3Fh

BCR43[15:8] (DATA_SCALE alias 0)

3Eh

BCR43[7:0] (Conf. Space. byte 47h 6 alias)

20h

41h

BCR44[15:8] (DATA_SCALE alias 0)

40h

BCR44[7:0] (Conf. Space. byte 47h 7 alias)

21h

43h

Checksum adjust byte for the 68 bytes of the

EEPROM contents. Checksum of the 68 bytes

of the EEPROM should total FFh.

42h

Reserved location: must be 00h

Unused locations - Ignored by device

3Fh

7Fh

Reserved

7Eh

Reserved

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