AMD

PRELIMINARY

1–24

Am79C982

X1

CRS

STR

CRS

AUI

CRS

TP0

CRS

TP1

CRS

TP2

CRS

TP3

CRS

TP4

CRS

TP5

CRS

TP6

CRS

TP7

CRS

AUI

TCK

(Note 1)

SO

(Note 2)

SO

AUI

SO

TP0

SO

TP1

SO

TP2

SO

TP3

SO

TP4

SO

TP5

SO

TP6

SO

TP7

SO

AUI

19406B-11

Notes:

1. Externally generated signal illustrates internal bIMR chip clock phase relationship.

2. For Minimum Mode

Figure 4. bIMR8 Management Port Minimum Mode and

Port Activity Monitor Signal Relationship

Q

bIMR4 Chip

XTAL

OSC

CK

D

Q

ASYNC

RESET

X1

RST

STR

CRS or

SO (Note)

CLR

CK

D

CK

SI

Shift Register

CK

T

P

3

T

P

2

T

P

1

T

P

0

A

U

I

19406B-12

Register

Q

CLR

CK

Q

D

Note: When used in minimum mode.

Q

Q

SHCK

Figure 5. bIMR4 LED Display Design using Minimum Mode

‘