AM8530H datasheet(13/194 Pages) AMD

13 / 194 page

General Information

AMD

1–5

1.3

BLOCK DIAGRAM

Figure 1–1 depicts the block diagram of the Am8530H and Figure 1–2 the block diagram

of the Am85C30. Data being received enters the receive data pins and follows one of

several data paths, depending on the state of the control logic. The contents of the regis-

ters and the state of the external control pins establish the internal control logic. Transmit-

ted data follows a similar pattern of control, register, and external pin definition.

Baud

Rate

Gen

Channel

Ch A

Reg

Int

Cont

Logic

Discrete

Control and

Status A

Discrete

Control and

Status B

Channel

Bus

I/O

Ch B

Reg

Int

Cont

Logic

Baud

Rate

Gen

Serial

Data

Wait/Request

SYNC

Channel Clocks

Modem, DMA,

Other Controls

Modem, DMA,

Other Controls

Serial

Data

Wait/ Request

SYNC

Channel Clocks

Internal Bus

Int

Cont

Lines

Cont

Data

07513C-001A

Figure 1–1. Am8530H Block Diagram

CPU

Bus I/O

Internal

Control

Logic

Interrupt

Control

Logic

Channel A

Registers

Channel B

Registers

Baud

Rate

Generator

10 x 19-Bit

Frame

Status

FIFO

Transmitter/

Receiver

Control

Logic

TxDA

RxDA

RTxCA

TRxCA

SYNCA

RTSA

CTSA

DCDA

Channel B

TxDB

RxDB

RTxCB

SYNCB

RTSB

CTSB

DCDB

TRxCB

Channel A

Data

Control

Interrupt

Control

Lines

Internal Bus

+5 V GND PCLK

10216A-001A

Figure 1–2. Am85C30 Block Diagram

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