SRK2000

Pin description

Doc ID 17811 Rev 2

3/17

1

Pin description

Figure 2.

Pin configuration

Table 2.

Pin description

n.

Name

Function

1SGND

Signal ground. Return of the bias current of the device and 0 V reference for

drain-to-source voltage monitors of both sections. Route this pin directly to

PGND.

2EN

Drain voltage threshold setting for synchronous rectifier MOSFET turn-off. UVLO

threshold programming. This pin is typically biased by either a pull-up resistor

connected to Vcc or by a resistor divider sensing Vcc. Pulling the pin to ground

disables the gate driver outputs GD1 and GD2 and can therefore be used also

as Enable input.

3

4

DVS1

DVS2

Drain voltage sensing for sections 1 and 2. These pins are to be connected to

the respective drain terminals of the corresponding synchronous rectifier

MOSFET via limiting resistors. When the voltage on either pin goes negative,

the corresponding synchronous rectifier MOSFET is switched on; as its

(negative) voltage exceeds a threshold defined by the EN pin, the MOSFET is

switched off. An internal logic rejects switching noise, however, extreme care in

the proper routing of the drain connection is recommended.

5

7

GD2

GD1

Gate driver output for sections 2 and 1. Each totem pole output stage is able to

drive Power MOSFETs with a peak current of 1 A source and 3.5 A sink. The

high-level voltage of these pins is clamped at about 12 V to avoid excessive gate

voltages in case the device is supplied with a high Vcc.

6PGND

Power ground. Return for gate-drive currents. Route this pin to the common

point where the source terminals of both synchronous rectifier MOSFETs are

connected.

8Vcc

Supply voltage of the device. A small bypass capacitor (0.1 µF typ.) to SGND,

located as close to the IC’s pins as possible, may be useful to obtain a clean

supply voltage for the internal control circuitry. A similar bypass capacitor to

PGND, again located as close to the IC’s pins as possible, may be an effective

energy buffer for the pulsed gate-drive currents.

GD2

SGND

EN

DVS1

DVS2

Vcc

GD1

PGND

1

2

3

4

8

7

6

5

GD2

SGND

EN

DVS1

DVS2

Vcc

GD1

PGND

1

2

3

4

8

7

6

5