Functional description

ST8024L

20/35

Doc ID 17709 Rev 5

6.3

Clock circuitry (only on SO-28 and TSSOP-28 packages)

The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from

a crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.

is made via inputs CLKDIV1 and CLKDIV2 (see Table 21).

The frequency change is synchronous, which means that during transition no pulse is

shorter than 45% of the smallest period, and that the first and last clock pulses regarding the

instant of change have the correct width.

When changing the frequency dynamically, the change is effective for only eight periods of

XTAL1. In order to reach a 45 to 55% duty factor on pin CLK, the input signal on pin XTAL1

should have a duty factor of 48 to 52% and transition times of less than 5% of the input

signal period.

If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit

layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin

CLK is guaranteed between 45 and 55% of the clock period.

The crystal oscillator runs as soon as the ST8024L is powered up. If the crystal oscillator is

used, or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card

as shown in the activation sequences in Figure 5 and Figure 6.

If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse is

applied to the card when it is sent by the system microcontroller (after completion of the

activation sequence).

Table 21.

1.

The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum

between changes is needed. The minimum duration of any state of CLK is eight periods of XTAL1.

CLKDIV1

CLKDIV2

00

01

11

10