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PIC16LF1906-ISOQTP 数据表(PDF) 80 Page - Microchip Technology |
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PIC16LF1906-ISOQTP 数据表(HTML) 80 Page - Microchip Technology |
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80 / 288 page  PIC16LF1904/6/7 DS41569A-page 80 Preliminary 2011 Microchip Technology Inc. 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared -TO bit of the STATUS register will not be set -PD bit of the STATUS register will not be cleared. • If the interrupt occurs during or after the execu- tion of a SLEEP instruction - SLEEP instruction will be completely exe- cuted - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared -TO bit of the STATUS register will be set -PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) CLKOUT(2) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC - 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(1) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h) Dummy Cycle PC + 2 0004h 0005h Dummy Cycle PC + 2 Note 1: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 118 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 118 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 118 PIE1 TMR1GIE ADIE RCIE TXIE — — —TMR1IE 73 PIE2 — — — — —LCDIE — — 74 PIR1 TMR1GIF ADIF RCIF TXIF — — — TMR1IF 75 PIR2 — — — — — LCDIF — — 76 STATUS — — —TO PD ZDC C 25 WDTCON — — WDTPS<4:0> SWDTEN 83 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode. |
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