STM32F207VC datasheet(170/178 Pages) STMICROELECTRONICS

170 / 178 page

Revision history

STM32F20xxx

170/178

DocID15818 Rev 11

22-Apr-2011

(continued)

Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and

tf(SCK) to tf(SCL) in Table 52: I2C characteristics and in Figure 40: I2C

bus AC waveforms and measurement circuit.

Added Table 57: USB OTG FS DC electrical characteristics and

updated Table 58: USB OTG FS electrical characteristics.

Updated VDD minimum value in Table 62: Ethernet DC electrical

characteristics.

Updated Table 66: ADC characteristics and RAIN equation.

Updated RAIN equation. Updated Table 68: DAC characteristics.

Updated tSTART in Table 69: TS characteristics.

Updated R typical value in Table 70: VBAT monitoring characteristics.

Updated Table 71: Embedded internal reference voltage.

Modified FSMC_NOE waveform in Figure 56: Asynchronous non-

multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of

FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK

period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-

AIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL-

NWEH), and updated data latency from 1 to 0 in Figure 60:

Synchronous multiplexed NOR/PSRAM read timings, Figure 61:

Synchronous multiplexed PSRAM write timings, Figure 62:

Synchronous non-multiplexed NOR/PSRAM read timings, and

Figure 63: Synchronous non-multiplexed PSRAM write timings,

Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV),

td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and

modified tw(CLK) minimum value in Table 76, Table 77, Table 78, and

Table 79.

Updated note 2 in Table 72, Table 73, Table 74, Table 75, Table 76,

Table 77, Table 78, and Table 79.

Modified th(NIOWR-D) in Figure 69: PC Card/CompactFlash controller

waveforms for I/O space write access.

Modified FSMC_NCEx signal in Figure 70: NAND controller

waveforms for read access, Figure 71: NAND controller waveforms for

write access, Figure 72: NAND controller waveforms for common

memory read access, and Figure 73: NAND controller waveforms for

common memory write access

Specified Full speed (FS) mode for Figure 89: USB OTG HS

peripheral-only connection in FS mode and Figure 90: USB OTG HS

host-only connection in FS mode.

Table 95. Document revision history (continued)

Date

Revision

Changes

STM32F207VC 数据表(PDF) 170 Page - STMicroelectronics

STM32F207VC 数据表(HTML) 170 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载