STM32F207VC datasheet(26/178 Pages) STMICROELECTRONICS

26 / 178 page

Functional overview

STM32F20xxx

26/178

DocID15818 Rev 11

Figure 7. Regulator OFF/internal reset OFF

The following conditions must be respected:

•

VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection

between power domains (see Figure 8).

•

PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V,

and until VDD reaches 1.7 V.

•

NRST should be controlled by an external reset controller to keep the device under

reset when VDD is below 1.7 V (see Figure 9).

In this mode, when the internal reset is OFF, the following integrated features are no more

supported:

•

The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.

•

The brownout reset (BOR) circuitry is disabled.

•

The embedded programmable voltage detector (PVD) is disabled.

•

VBAT functionality is no more available and VBAT pin should be connected to VDD.

REGOFF

VCAP_1

ai18477b

VCAP_2

NRST

1.2 V

IRROFF

VDD

1.2 V

VDD

External VDD/VCAP_1/2

power supply supervisor

Ext. reset controller active

when VDD<1.7V and

VCAP_1/2 < 1.08 V

PA0

STM32F207VC 数据表(PDF) 26 Page - STMicroelectronics

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