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STM32F373VC 数据表(PDF) 105 Page - STMicroelectronics |
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STM32F373VC 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 131 page ![]() DocID022691 Rev 4 105/131 STM32F37xxx Electrical characteristics 114 6.3.21 VBAT monitoring characteristics 6.3.22 Timer characteristics The parameters given in Table 68 are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 67. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT -50- K Ω Q Ratio on VBAT measurement - 2 - Er(1) 1. Guaranteed by design, not tested in production. Error on Q -1 - +1 % TS_vbat(2) 2. Shortest sampling time can be determined in the application by multiple iterations. ADC sampling time when reading the VBAT 1mV accuracy 5- - µs Table 68. TIMx(1) (2)characteristics 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14, TIM15, TIM16 , TIM17, TIM18 and TIM19 timers. 2. Data based on characterization results, not tested in production. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time 1- tTIMxCLK fTIMxCLK = 72 MHz 13.9 - ns fEXT Timer external clock frequency on CH1 to CH4 0fTIMxCLK/2 MHz fTIMxCLK = 72 MHz 0 24 MHz ResTIM Timer resolution TIMx (except TIM2) -16 bit TIM2 - 32 tCOUNTER 16-bit counter clock period 1 65536 tTIMxCLK fTIMxCLK = 72 MHz 0.0139 910 µs tMAX_COUN T Maximum possible count with 32-bit counter - 65536 × 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.65 s Table 69. IWDG min/max timeout period at 40 kHz (LSI) (1)(2) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 |
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