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STM32L151VD 数据表(PDF) 107 Page - STMicroelectronics |
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STM32L151VD 数据表(HTML) 107 Page - STMicroelectronics |
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107 / 140 page  STM32L151xD STM32L152xD Electrical characteristics Doc ID 022027 Rev 6 107/140 6.3.17 I2S characteristics Note: Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. Table 58. I2S characteristics Symbol Parameter Conditions Min Max Unit fMCK I2S Main Clock Output 256 x 8K 256xFs (1) 1. The maximum for 256xFs is 8 MHz MHz fCK I2S clock frequency Master data: 32 bits - 64xFs MHz Slave data: 32 bits - 64xFs DCK I2S clock frequency duty cycle Slave receiver, 48KHz 30 70 % tr(CK) I2S clock rise time Capacitive load CL=30pF - 8 ns tf(CK) I2S clock fall time 8 tv(WS) WS valid time Master mode 4 24 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 15 - th(WS) WS hold time Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 8 - tsu(SD_SR) Data input setup time Slave receiver 9 - th(SD_MR) Data input hold time Master receiver 5 - th(SD_SR) Slave receiver 4 - tv(SD_ST) Data output valid time Slave transmitter (after enable edge) -64 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 22 - tv(SD_MT) Data output valid time Master transmitter (after enable edge) -12 th(SD_MT) Data output hold time Master transmitter (after enable edge) 8- |
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