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STM32L151VD 数据表(PDF) 109 Page - STMicroelectronics |
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STM32L151VD 数据表(HTML) 109 Page - STMicroelectronics |
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109 / 140 page  STM32L151xD STM32L152xD Electrical characteristics Doc ID 022027 Rev 6 109/140 6.3.18 SDIO characteristics Figure 33. SDIO timings Table 59. SDIO characteristics(1) 1. Based on characterization, not tested in production. Symbol Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL ≤ 30 pF 0 24 MHz tW(CKL) Clock low time, fPP = 24 MHz CL ≤ 30 pF 20(2) 2. Values measured with a threshold level equal to VDD/2. - ns tW(CKH) Clock high time, fPP = 24 MHz CL ≤ 30 pF 18(2) - tr Clock rise time, fPP = 24 MHz CL ≤ 30 pF - 5 tf Clock fall time, fPP = 24 MHz CL ≤ 30 pF - 5 CMD, D inputs (referenced to CK) in SD default mode From 2.8 to 3.6 V tISU Input setup time, fPP = 24 MHz CL ≤ 30 pF 2 - ns tIH Input hold time, fPP = 24 MHz CL ≤ 30 pF 1.6 - CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time, fPP = 24 MHz CL ≤ 30 pF 0 14 ns tOHD Output hold default time, fPP = 24 MHz CL ≤ 30 pF 0 - tW(CKH) CK D, CMD(output) D, CMD(input) tC tW(CKL) tOVD tISU tIH tf tr tOHD MS31068V1 |
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