ADA4841-1/ADA4841-2

Rev. E | Page 13 of 20

THEORY OF OPERATION

AMPLIFIER DESCRIPTION

The ADA4841-1/ADA4841-2 are low power, low noise,

precision voltage-feedback op amps for single or dual voltage

supply operation. The ADA4841-1/ADA4841-2 are fabricated

on ADI’s second generation XFCB process and feature trimmed

supply current and offset voltage. The 2.1 nV/√Hz voltage noise

(very low for a 1.1 mA supply current amplifier), 40 μV offset

voltage, and sub 1 μV/°C offset drift is accomplished with an

input stage made of an undegenerated PNP input pair driving a

symmetrical folded cascode. A rail-to-rail output stage provides

the maximum linear signal range possible on low voltage

supplies and has the current drive capability needed for the

relatively low resistance feedback networks required for low

noise operation. CMRR, PSRR, and open-loop gain are all

typically above 100 dB, preserving the precision performance in

a variety of configurations. Gain bandwidth is kept high for this

power level to preserve the outstanding linearity performance

for frequencies up to 100 kHz. The ADA4841-1 has a power-

down function to further reduce power consumption. All this

results in a low noise, power efficient, precision amplifier that is

well-suited for high resolution and precision applications.

DC ERRORS

Figure 39 shows a typical connection diagram and the major dc

error sources. The ideal transfer function (all error sources set

to 0 and infinite dc gain) can be written as

IN

G

F

IP

G

F

OUT

V

R

R

V

R

R

V

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

= 1

(1)

Figure 39. Typical Connection Diagram and DC Error Sources

This reduces to the familiar forms for inverting and

noninverting op amp gain expressions

IP

G

F

OUT

V

R

R

V

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

= 1

(2)

IN

G

F

OUT

V

R

R

V

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ −

=

(3)

The total output voltage error is the sum of errors due to the

amplifier offset voltage and input currents. The output error

due to the offset voltage can be estimated as

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

×

⎟

⎠

⎞

⎜

⎝

⎛

+

−

+

+

=

G

F

OUT

PNOM

P

OFFSET

OUT

R

R

A

V

PSRR

V

V

CMRR

VCM

V

V

NOM

ERROR

1

(4)

where:

NOM

OFFSET

V

is the offset voltage at the specified supply voltage.

This is measured with the input and output at midsupply.

VCM is the common-mode voltage.

NOM

p

V

is the specified power supply voltage.

CMRR is the common-mode rejection ratio.

PSRR is the power supply rejection ratio.

A is the dc open-loop gain.

The output error due to the input currents can be estimated as

+

−

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

×

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

×

=

B

G

F

S

B

G

F

G

F

OUT

I

R

R

R

I

R

R

R

R

V

ERROR

1

1

)

||

(

(5)

error due to the input bias current.

NOISE CONSIDERATIONS

Figure 40 illustrates the primary noise contributors for the

typical gain configurations. The total rms output noise is

the root-mean-square of all the contributions.

ien

ien

+ vout_en –

ven

Figure 40. Noise Sources in Typical Connection