ADA4841-1/ADA4841-2

Rev. E | Page 15 of 20

Figure 45 shows the amplifier frequency response as a G = −1

inverter with the input and output stage biased near the

negative supply rail.

6

–12

0.1

100

FREQUENCY (MHz)

110

3

0

–3

–6

–9

G = –1

Figure 45. Small Signal Frequency Response vs. Negative Supply Bias

from −200 mV to −20 mV. With the input and output voltages

biased 200 mV above the bottom rail, the G = −1 inverter

frequency response is not much different from what is seen

with the input and output voltages biased near midsupply.

At 150 mV bias, the frequency response starts to decrease

and at 20 mV, the inverter bandwidth is less than half its

nominal value.

CAPACITANCE DRIVE

Capacitance at the output of an amplifier creates a delay within

the feedback path that, if within the bandwidth of the loop, can

create excessive ringing and oscillation. The G = +1 follower

topology has the highest loop bandwidth of any typical

configuration and, therefore, is the most vulnerable to the

effects of capacitance load.

A small resistor in series with the amplifier output and the

capacitive load mitigates the problem. Figure 46 plots the

recommended series resistance vs. capacitance for gains

of +1, +2, and +5.

60

0

10

10000

CAPACITANCE LOAD (pF)

50

40

30

20

10

100

1000

G = +1

G = +2

G = +5

Figure 46. Series Resistance vs. Capacitance Load

INPUT PROTECTION

The ADA4841-1/ADA4841-2 are fully protected from ESD

events, withstanding human body model ESD events of 2.5 keV

and charge device model events of 1 keV with no measured

performance degradation. The precision input is protected

with an ESD network between the power supplies and diode

clamps across the input device pair, as shown in Figure 47.

VP

ESD

ESD

VEE

VCC

BIAS

TO REST OF AMPLIFIER

VN

ESD

ESD

Figure 47. Input Stage and Protection Diodes

For differential voltages above approximately 1.4 V, the diode

clamps start to conduct. Too much current can cause damage

due to excessive heating. If large differential voltages need to be

sustained across the input terminals, it is recommended that the

current through the input clamps be limited to below 150 mA.

Series input resistors sized appropriately for the expected

differential overvoltage provide the needed protection.

The ESD clamps start to conduct for input voltages more than

0.7 V above the positive supply and input voltages more than

0.7 V below the negative supply. It is recommended that the

fault current be limited to less than 150 mA if an overvoltage

condition is expected.