ZSC31150

Fast Automotive Sensor Signal Conditioner

Data Sheet

August 31, 2010

© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.07

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without

notice.

15 of 24

2.5.

System Control and Conditioning Calculation

The system control supports the following tasks/features:



control the measurement cycle regarding to the EEPROM-stored configuration data



16 bit correction calculation for each measurement signal using the EEPROM stored calibration

coefficients and ROM-based algorithms = signal conditioning



manage start up sequence and start signal conditioning



handle communication requests received by the digital interface



failsafe tasks for the functions of ZSC31150 and message detected errors with diagnostic states

Refer 'ZSC31150 Functional Description' for a detailed description.

2.5.1.

Operation Modes

The internal state machine represents three main states:



the continuous running signal conditioning mode – called Normal Operation Mode: NOM



the calibration mode with access to all internal registers and states – called Command Mode: CM



the failure messaging mode – called Diagnostic Mode: DM

2.5.2.

Start Up Phase

17

The start up phase consists of following parts:

1. internal supply voltage settling phase (=potential VDDA-VSSA) – finished by disabling the reset signal

through the power on clear block (POC). Refer 'ZSC31150 High Voltage Protection Description',

chapter 4 for power on/off thresholds.

Time (for beginning with VDDA-VSSA=0V): 500µs to 2000µs, AOUT: tristate

2. system start, EEPROM read out and signature check (and ROM-check, if CFGAPP:CHKROM=1).

Time: ~200µs (~9000µs with ROM-check – 28180clocks ), AOUT: LOW (DM)

3. processing the start routine of signal conditioning (all measures & conditioning calculation).

Time: 5x AD conversion time, AOUT behavior depending on adjusted OWI mode (refer 2.6):

- OWIANA & OWIDIS => AOUT: LOW (DM)

- OWIWIN & OWIENA => AOUT: tristate

The analog output AOUT will be activated at the end of start up phase depending on adjusted output and

communication mode (refer section 2.6). In case of detected errors Diagnostic Mode (DM) is activated and

diagnostic output signal is driven at the output.

After the start up phase the continuous running measurement and calibration cycle is started. Refer

'ZSC31150 Bandwidth Calculation Sheet' for detailed information about output update rate.

2.5.3.

Conditioning Calculation

The digitalized value for pressure (acquired raw data) is processed with the correction formula to remove

offset and temperature dependency and to compensate non-linearity up to 3rd order. The result of the

correction calculation is a non-negative 15 Bit value for pressure (P) in the range [0; 1). This value P is clipped

with programmed limitation coefficients and continuously written to the output register of the digital serial

interface and the output DAC.

Note:

The conditioning includes up to third order nonlinearity sensor input correction. The available

adjustment ranges depend on the specific calibration parameters, for a detailed description refer to

'ZSC31150 Functional Description'. To give a rough idea: Offset compensation and linear

correction are only limited by the loose of resolution it will cause, the second order correction is

possible up to about 30% full scale difference to straight line, third order up to about 20% (ADC

resolution = 13bit). The used calibration principle is able to reduce present nonlinearity errors of

17

All described timings are roughly estimated values and correlates with internal clock frequency. Timings estimated for fclk=3MHz.