DSPIC33FJ64GP706 datasheet(129/322 Pages) MICROCHIP

129 / 322 page

DS70286C-page 127

dsPIC33FJXXXGPX06/X08/X10

8.0

DIRECT MEMORY ACCESS

(DMA)

Direct Memory Access (DMA) is a very efficient

mechanism of copying data between peripheral SFRs

(e.g., UART Receive register, Input Capture 1 buffer),

and buffers or variables stored in RAM, with minimal

CPU

intervention.

The

DMA

controller

can

automatically copy entire blocks of data without

requiring the user software to read or write the

peripheral Special Function Registers (SFRs) every

time a peripheral interrupt occurs. The DMA controller

uses a dedicated bus for data transfers and therefore,

does not steal cycles from the code execution flow of

the CPU. To exploit the DMA capability, the

corresponding user buffers or variables must be

located in DMA RAM.

The dsPIC33FJXXXGPX06/X08/X10 peripherals that

can utilize DMA are listed in Table 8-1 along with their

associated Interrupt Request (IRQ) numbers.

TABLE 8-1:

PERIPHERALS WITH DMA

SUPPORT

The DMA controller features eight identical data

transfer channels.

Each channel has its own set of control and status

registers. Each DMA channel can be configured to

copy data either from buffers stored in dual port DMA

RAM to peripheral SFRs, or from peripheral SFRs to

buffers in DMA RAM.

The DMA controller supports the following features:

• Word or byte sized data transfers.

• Transfers from peripheral to DMA RAM or DMA

RAM to peripheral.

• Indirect Addressing of DMA RAM locations with or

without automatic post-increment.

• Peripheral Indirect Addressing – In some

peripherals, the DMA RAM read/write addresses

may be partially derived from the peripheral.

• One-Shot Block Transfers – Terminating DMA

transfer after one block transfer.

• Continuous Block Transfers – Reloading DMA

RAM buffer start address after every block

transfer is complete.

• Ping-Pong Mode – Switching between two DMA

RAM start addresses between successive block

transfers, thereby filling two buffers alternately.

• Automatic or manual initiation of block transfers

• Each channel can select from 20 possible

sources of data sources or destinations.

For each DMA channel, a DMA interrupt request is

generated when a block transfer is complete.

Alternatively, an interrupt can be generated when half of

the block has been filled.

Note:

This data sheet summarizes the features

of the dsPIC33FJXXXGPX06/X08/X10

family of devices. However, it is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to Section 22.

“Direct

Memory

Access

(DMA)”

(DS70182) in the “dsPIC33F Family

Reference Manual”, which is available

from

the

Microchip

web

site

(www.microchip.com).

Peripheral

IRQ Number

INT0

Input Capture 1

Input Capture 2

Output Compare 1

Output Compare 2

Timer2

Timer3

SPI1

SPI2

UART1 Reception

UART1 Transmission

UART2 Reception

UART2 Transmission

ADC1

ADC2

DCI

ECAN1 Reception

ECAN1 Transmission

ECAN2 Reception

ECAN2 Transmission

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