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数据搜索系统，热门电子元器件搜索 |
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DSPIC33FJ64GP706 数据表(PDF) 130 Page - Microchip Technology |
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DSPIC33FJ64GP706 数据表(HTML) 130 Page - Microchip Technology |
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130 / 322 page  dsPIC33FJXXXGPX06/X08/X10 DS70286C-page 128 © 2009 Microchip Technology Inc. FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS 8.1 DMAC Registers Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7) contains the following registers: • A 16-bit DMA Channel Control register (DMAxCON) • A 16-bit DMA Channel IRQ Select register (DMAxREQ) • A 16-bit DMA RAM Primary Start Address Offset register (DMAxSTA) • A 16-bit DMA RAM Secondary Start Address Offset register (DMAxSTB) • A 16-bit DMA Peripheral Address register (DMAxPAD) • A 10-bit DMA Transfer Count register (DMAxCNT) An additional pair of status registers, DMACS0 and DMACS1, are common to all DMAC channels. CPU SRAM DMA RAM CPU Peripheral DS Bus Peripheral 3 DMA Peripheral Non-DMA SRAM X-Bus PORT 2 PORT 1 Peripheral 1 DMA Ready Peripheral 2 DMA Ready Ready Ready DMA DS Bus CPU DMA CPU DMA CPU DMA Peripheral Indirect Address Note: CPU and DMA address buses are not shown for clarity. DMA Controller DMA Channels |
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