64GA106 datasheet(74/330 Pages) MICROCHIP

74 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 74

 2010 Microchip Technology Inc.

7.3

Interrupt Control and Status

Registers

The PIC24FJ256GA110 family of devices implements

a total of 37 registers for the interrupt controller:

• INTCON1

• INTCON2

• IFS0 through IFS5

• IEC0 through IEC5

• IPC0 through IPC23 (except IPC14 and IPC17)

•INTTREG

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the Inter-

rupt Nesting Disable (NSTDIS) bit, as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The IFSx registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit which is

set by the respective peripherals, or an external signal,

and is cleared via software.

The IECx registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPCx registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

The INTTREG register contains the associated inter-

rupt vector number and the new CPU interrupt priority

level, which are latched into the Vector Number

(VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit

fields in the INTTREG register. The new interrupt

priority level is the priority of the pending interrupt.

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the order of their vector numbers,

as shown in Table 7-2. For example, the INT0 (External

Interrupt 0) is shown as having a vector number and a

natural order priority of 0. Thus, the INT0IF status bit is

found in IFS0<0>, the INT0IE enable bit in IEC0<0>

and the INT0IP<2:0> priority bits in the first position of

IPC0 (IPC0<2:0>).

Although they are not specifically part of the interrupt

control hardware, two of the CPU control registers con-

tain bits that control interrupt functionality. The ALU

STATUS Register (SR) contains the IPL<2:0> bits

(SR<7:5>); these indicate the current CPU interrupt

priority level. The user may change the current CPU

priority level by writing to the IPL bits.

The CORCON register contains the IPL3 bit, which

together with IPL<2:0>, indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

All interrupt registers are described in Register 7-1

through Register 7-38, on the following pages.

Timer1

00001Ah

00011Ah

IFS0<3>

IEC0<3>

IPC0<14:12>

Timer2

000022h

000122h

IFS0<7>

IEC0<7>

IPC1<14:12>

Timer3

000024h

000124h

IFS0<8>

IEC0<8>

IPC2<2:0>

Timer4

00004Ah

00014Ah

IFS1<11>

IEC1<11>

IPC6<14:12>

Timer5

00004Ch

00014Ch

IFS1<12>

IEC1<12>

IPC7<2:0>

UART1 Error

000096h

000196h

IFS4<1>

IEC4<1>

IPC16<6:4>

UART1 Receiver

00002Ah

00012Ah

IFS0<11>

IEC0<11>

IPC2<14:12>

UART1 Transmitter

00002Ch

00012Ch

IFS0<12>

IEC0<12>

IPC3<2:0>

UART2 Error

000098h

000198h

IFS4<2>

IEC4<2>

IPC16<10:8>

UART2 Receiver

000050h

000150h

IFS1<14>

IEC1<14>

IPC7<10:8>

UART2 Transmitter

000052h

000152h

IFS1<15>

IEC1<15>

IPC7<14:12>

UART3 Error

0000B6h

0001B6h

IFS5<1>

IEC5<1>

IPC20<6:4>

UART3 Receiver

0000B8h

0001B8h

IFS5<2>

IEC5<2>

IPC20<10:8>

UART3 Transmitter

0000BAh

0001BAh

IFS5<3>

IEC5<3>

IPC20<14:12>

UART4 Error

0000C2h

0001C2h

IFS5<7>

IEC5<7>

IPC21<14:12>

UART4 Receiver

0000C4h

0001C4h

IFS5<8>

IEC5<8>

IPC22<2:0>

UART4 Transmitter

0000C6h

0001C6h

IFS5<9>

IEC5<9>

IPC22<6:4>

TABLE 7-2:

IMPLEMENTED INTERRUPT VECTORS (CONTINUED)

Interrupt Source

Vector

Number

IVT Address

AIVT

Address

Interrupt Bit Locations

Flag

Enable

Priority

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