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64GA106 数据表(PDF) 75 Page - Microchip Technology

部件名 64GA106
功能描述  64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers
PDF  330 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

64GA106 数据表(HTML) 75 Page - Microchip Technology

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 2010 Microchip Technology Inc.
DS39905E-page 75
PIC24FJ256GA110 FAMILY
REGISTER 7-1:
SR: ALU STATUS REGISTER (IN CPU)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—DC(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL2(2,3)
IPL1(2,3)
IPL0(2,3)
RA(1)
N(1)
OV(1)
Z(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
IPL<2:0>:
CPU Interrupt Priority Level Status bits(2,3)
111
= CPU interrupt priority level is 7 (15). User interrupts disabled.
110
= CPU interrupt priority level is 6 (14)
101
= CPU interrupt priority level is 5 (13)
100
= CPU interrupt priority level is 4 (12)
011
= CPU interrupt priority level is 3 (11)
010
= CPU interrupt priority level is 2 (10)
001
= CPU interrupt priority level is 1 (9)
000
= CPU interrupt priority level is 0 (8)
Note 1:
See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2:
The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3:
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 7-2:
CORCON: CPU CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
R/W-0
U-0
U-0
—
—
—
—IPL3(2)
PSV(1)
—
—
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 3
IPL3:
CPU Interrupt Priority Level Status bit(2)
1
= CPU interrupt priority level is greater than 7
0
= CPU interrupt priority level is 7 or less
Note 1:
See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2:
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.



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