Product Brief AS3510

Rev. 1v2, June 2004

CONFIDENTIAL

Page 3 of 19

Modes of Operation

Inputs

Outputs

LDO-Modes

ENLDO12

ENLDO3

DVDD, AVDD

PVDD

OFF

LL

LDO1, LDO2 are OFF

2.8–3.6V supply fr. Ext.

LDO3 is OFF

1.75-3.6V supply fr. Ext.

ON_12

HL

LDO1, LDO2 are ON

Output is 2.9Vtyp

LDO3 is OFF

1.75-3.6V supply fr. Ext.

or connected to DVDD

ON_123

HH

LDO1, LDO2 are ON

Output is 2.9Vtyp

LDO3 is ON

Output 2.5Vtyp

Table 1

LDO Operating Modes

Nodes:

-

1. BVDD as input to the LDO regulators has to be >=3.0V.

-

2. DVDD - AVDD max. difference of 100mV.

-

3. PVDD has to be lower or equal to DVDD.

-

4. LDO1 is to be used for regulating AVDD (connect pin 25 to pin 26)

-

5. LDO2 output is internaly connected to DVDD (pos. digital supply)

-

6. LDO3 output is internaly connected to PVDD (pos. peripheral supply)

Inputs

Outputs

DAC-Modes

DACPD

I2S

Gain3:0

OUTR, OUTL

OFF

H

X

LLLL

TriState

DAC_ON

L

LRCK up to 50kHz

MCLK … 128*F(LRCK)

SCLK L=>H strobes SDI

SCLK … >=38*F(LRCK)

SDI left justified with MSB first

LLLL

TriState

AUDIO_ON

L

LRCK up to 50kHz

MCLK … 128*F(LRCK)

SCLK L=>H strobes SDI

SCLK … >=38*F(LRCK)

SDI left justified with MSB first

LLLH

.

.

HHHH

Stereo audio output

with PowerAmp gain adjusted

in 3dB steps by GAIN(3:0)

Table 2

DAC Operating Modes

Nodes:

-

During supply voltages settling at system start-up GAIN(3:0) should be held “L”.

-

The MCLK frequency ratio to LRCK is permanently checked. If the ratio is different to 128, the DAC goes in Reset-Mode (no

audio will betransferred).

-

MCLK rising edge should not be within +/-10ns of LRCK edges.

-

Capacitors at VREF, AGND and BGND are needed for the DAC operation.

-

The SCLK has to have at least 34 or 38 cycles within one LRCK cycle

2*(16bit data + the leading empty bit) or 2*(18bit data + the leading empty bit)

-

There can be more SDI bits presented but just the first 18 bits are transferred.