Product Brief AS3510

Rev. 1v2, June 2004

CONFIDENTIAL

Page 4 of 19

Inputs

Output

ADC-Modes

ENADC

I2S-Clocks

LRCK, SCLK,MCLK

MICP/MICN

SDO

OFF

L

X

X

static L

ADC_ON

H

LRCK up to 50kHz

MCLK … 128*F(LRCK)

SCLK … >=34*F(LRCK)

Differential analog

input

to be converted to

digital output

SDI serial data output

Ieft justified to LRCK with

edge

Table 3

ADC Operating Modes

Nodes:

-

There are 16bit presented at SDO at each cycle but just the first 14 do have relevalt data.

-

The ADC is a single channel (mono) path. The same SDO bitstream is presented for left and right channel of one cycle.

-

-

SCLK has to have at least 34 cycles within one LRCK cycle

2*(16bit data + the leading empty bit)