AS3543 datasheet(75/92 Pages) AMSCO

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Revision 1.11

74 - 91

AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 74. PLL Register

Name

Base

Default

PLL

2-wire serial

00h

Offset: 1Ah-7

PLL Register

This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

7:4

OSR<3:0>

0000

R/W

Sets the oversampling rate when using the internal PLL

0x0: 128

0x1-0xF: n/a

3:2

VCO_MODE<1:0>

R/W

Selects the speed of the PLL VCO according to the audio

sampling frequency.

00: normal: 24-48kHz

01: low: 8-23kHz

10: high: 49-96kHz

11: n/a

1:0

PLL_MODE<1:0>

R/W

Selects the PLL mode and master clock frequency source

00: automatic

turns PLL on, PLL clock is used as master clock if freq(LRCK)

>8kHz and freq(MCLK)<32*freq(LRCK)

01: ON; turns PLL on, PLL clock is used as master clock

10: OFF; turns the PLL off, MCLK is used as master clock

11: auto_inv; like automatic but with inverted clock

Table 75. DCDC15 Register

Name

Base

Default

DCDC15

2-wire serial

00h

Offset: 1Bh-1

DCDC15 Register

This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

DIM_UP_XDOWN

R/W

0: disables the step-up converter and dims it down

1: enables the step-up converter and dims it up

6:5

DIM_RATE<1:0>

R/W

Selects the dimming speed when enabling or disablilng the

DCDC15

00: 0ms

01: 300ms

10: 600ms

11: 1200ms

VFB_ON

R/W

0: current feedback selected via ISINK1 and ISINK2

1: voltage feedback selected, ISINK1 is sinking 50uA to define

the voltage via an external zener diode

ExtDim_ON

R/W

0: selects internal clock for dimming

1: selects external clock for dimming

2:0

000

n/a

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