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AS3676 数据表(PDF) 76 Page - ams AG |
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AS3676 数据表(HTML) 76 Page - ams AG |
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76 / 92 page ![]() www.austriamicrosystems.com/AS3676 1v1-4 75 - 91 AS3676 Datasheet - D e ta i l e d D e s c r i p t i o n 8.9 Power-On Reset The internal reset is controlled by two sources: VBAT Supply Serial interface state (CLK, DATA) The internal reset is forced if VBAT is low or if both interface pins (CLK, DATA) are low for more than tPOR_DEB (typ. 100ms) 6. Then device enters shutdown mode. For details see section Operating Modes on page 80. The reset levels control the state of all registers. As long as VBAT and CLK/DATA are below their reset thresholds, the register contents are set to default. Access by serial interface is possible once the reset thresholds are exceeded. Figure 33. Zero Power Device Wakeup block diagram 5:4 audio_source 00b R/W Audio Buffer input source 00 CURR33 01 DCDC_FB 10 GPIO1/DLS 11 GPIO2/LIGHT 6. Only if shutdwn_enab=1 Table 115. Power On Reset Parameters Symbol Parameter Condition Min Typ Max Unit VPOR_VBAT Overall Power-On Reset Monitor voltage on V2_5; power-on reset for all internal functions. 1.8 2.15 2.4 1 V Table 114. Audio Control 2 Register (Continued) Addr: 55h Audio Control 2 Audio Mode Control Register Bit Bit Name Default Access Description !" # $ %& ' ()% ** ( + * +% , ,(,( &" ( * -' . / -' / ( ()% *" / -' -' / AS3676 |
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