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AS5048 数据表(PDF) 21 Page - ams AG |
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AS5048 数据表(HTML) 21 Page - ams AG |
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21 / 30 page  Revision 1.3 www.austriamicrosystems.com/AS504 8 Page 20 of 29 AS5048A/AS5048B Magnetic Rotary Encoder 14-bit Angular Position Sensor Datasheet 4.3.2 I²C Timing FS-mode+ HS-mode CB=100pF HS-mode CB=400pF (5) Symbol Parameter Condition Min Max Min Max Min Max Unit fSCLK SCL clock Frequency -- 1000 -- 3400 -- 1700 kHz tBUF Bus Free Time; time between STOP and START Condition 500 -- 500 -- 500 -- ns tHD;STA Hold Time; (Repeated) START Condition (1) 260 -- 160 -- 160 -- ns tLOW LOW Period of SCL Clock 500 -- 160 -- 320 -- ns tHIGH HIGH Period of SCL Clock 260 -- 60 -- 120 -- ns tSU;STA Setup Time for a Repeated START condition 260 -- 160 -- 160 -- ns tHD;DAT Data Hold Time (2) 0 450 0 70 0 150 ns tSU;DAT Data Setup Time (3) 50 -- 10 -- 10 -- ns tR Rise Time of SDA and SCL Signals 20+0.1 Cb 120 -- -- -- -- ns tF Fall time of SDA and SCL signals 20+0.1 Cb 120 (4) -- -- -- -- ns trCL Rise time of SCLH signal Ext. pull-up source of 3mA -- -- 10 40 20 80 ns trCL1 Rise time of SCLH signal after repeated START condition and after an acknowledge bit Ext. pull-up source of 3mA -- -- 10 80 20 160 ns tfCL Output rise time of SCLH signal Ext. pull-up source of 3mA -- -- 10 40 20 80 ns trDA Output rise time of SDAH signal -- -- 10 80 20 160 ns tfDA Output rise time of SDAH signal -- -- 10 80 20 160 ns tSU;STO Setup Time for STOP Condition 260 -- 160 -- 160 -- ns VnL Noise margin at LOW level 0.1VDDp -- 0.1VDDp -- 0.1VDDp -- V VnH Noise margin at HIGH level 0.2VDDp -- 0.2VDDp -- 0.2VDDp -- V Table 1 5 I²C Timing (1) after this time the first clock is generated (2) A device must internally provide a minimum hold time (120ns / max 250ns for Fast-mode Plus, 80ns / max 150ns for High- speed mode) for the SDA signal (referred to the VIHmin of the SCL) to bridge the undefined region of the falling edge of SCL. (3) A fast-mode device can be used in standard-mode system, but the requirement tSU;DAT = 250ns must then e met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does strech the LOW period of the SCL signal, it must output the next data bit to the SDA line tRmax + TSU;DAT = 1000 + 250 = 1250ns before the SCL line is released. (4) In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be considered for bus timing (5) For capacitive bus loads between 100pF and 400pF, the timing parameters must be linearly interpolated |
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