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AS5215

Datasheet - Electrical Character i s t ics

6.1 Timing Characteristics

Remark: The digital interface will be reset during the low phase of the CS signal.

SF=AP1_

1/AP2_1

Amplitude ratio mismatch at room

temperature

-2

2

%

DC Offset

0.294

0.3

0.306

0.49

0.5

0.51

DC Offset Drift

-40 to 150ºC

-50

+50

µV/ºC

THD

Total Harmonic Distortion

0.2

%

SR

Slew Rate

1

V/µs

Capacitive Load

1000

pF

Table 7. Timing Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Unit

t1_3

Chip select to positive edge of DCLK

30

-

ns

t2_3

Chip select to drive bus externally

0-

ns

t3

Setup time command bit

Data valid to positive edge of DCLK

30

-

ns

t4

Hold time command bit

Data valid after positive edge of DCLK

15

-

ns

t5

Float time

Positive edge of DCLK for last command bit to bus float

-

DCLK/

2+0

ns

t6

Bus driving time

Positive edge of DCLK for last command bit to bus

drive

DCLK/

2+0

-ns

t7

Data valid time

Positive edge of DCLK to bus valid

DCLK/

2+0

DCLK/

2+30

ns

t8

Hold time data bit

Data valid after positive edge of DCLK

DCLK/

2+0

-ns

t9_3

Hold time chip select

Positive edge DCLK to negative edge of chip select

DCLK/

2+0

-ns

t10_3

Bus floating time

Negative edge of chip select to float bus

-30

ns

t11

Setup time data bit at write access

Data valid to positive edge of DCLK

30

-

ns

t12

Hold time data bit at write access

Data valid after positive edge of DCLK

15

-

ns

t13_3

Bus floating time

Negative edge of chip select to float bus

-30

ns

Table 6. Electrical System Specifications

Symbol

Parameter

Condition

Min

Typ

Max

Unit