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Revision 2.3

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AS8525

Datasheet - Detailed Descr i p ti on

7.4 LIN Transceiver

The device has a LIN transceiver with slew-controlled bus driver for controlling the electromagnetic emissions from the LIN bus. Further, the slew

rate is independent of the bus load. The transmitter relays the data from the LIN controller (TX pin) to the bus (LIN pin), and the receiver provides

the data on the bus to the controller (RX pin). The transceiver conforms to the LIN 2.1 standard.

The LIN transceiver has a timeout watchdog for TX. After the timeout, the LIN bus will be released to the recessive state from the dominant state.

The bus driver has an inbuilt short-circuit current limitation facility to protect the device from damage when there is a short between the bus and

the supply.

In addition to the data receiver, there is a low-power receiver active in the device standby/sleep mode which received a wake-up event from the

bus to bring the device to normal mode.

7.5 Temperature Monitor / Limiter

The temperature limiter circuit powers down the device when the junction temperature exceeds 170°C (nominal). It also issues an over-

temperature warning at 160°C (nominal). The device is powered up again when the junction temperature falls below 140°C (nominal). The over-

temperature warning flag is also cleared at this temperature.

The temperature limiter circuit can be optionally disabled through SPI.

7.6 VSUP Under-Voltage Reset

When VSUP drops below VSUVR_ON, the RESET_VSUP_N switches back to low level. This is treated as a master reset and will have the

highest priority over all other signals. In this case, the regulators, LIN transceiver, and all other blocks are shut off, and the device comes to a

complete stop. The device returns to the normal mode when VSUP rises over VSUVR_OFF again irrespective of the mode it was in prior to this

under-voltage condition.

7.7 RESET

RESET module generates an active-low reset signal for the external circuitry supplied by VCC. The behavior of the reset output is depicted in

Figure 6 in different cases. As shown, RESET signal is affected by an under-voltage condition on VCC and Watchdogs which are described in

detail in the subsequent sections.

The reset period can be one-time programmed to 4, 16, and 32 ms with a default value of 8 ms.

Figure 6. Reset Functionality

VCC

VSUP

VUVR_OFF

T>Tj

T<Tj

RESET

Start-up

Over-temp

Shutdown

Glitch in

VSUP

VSUP UV

SC Current

Limitation Active

VUVR_ON

Reset by

Watchdog