AT45DB321

2

ries that are accessed randomly with multiple address lines

and a parallel interface, the DataFlash uses a serial inter-

face to sequentially access its data. The simple serial inter-

face facilitates hardware layout, increases syste m

reliability, minimizes switching noise, and reduces package

size and active pin count. The device is optimized for use in

many commercial and industrial applications where high

density, low pin count, low voltage, and low power are

essential. Typical applications for the DataFlash are digital

voice storage, image storage, and data storage. The

device operates at clock frequencies up to 13 MHz with a

typical active read current consumption of 4 mA.

To allow for simple in-system reprogrammability, the

AT45DB321 does not require high input voltages for pro-

gramming. The device operates from a single power sup-

ply, 2 . 7 V t o 3 . 6 V , for bot h th e p r ogr a m a nd r ead

operations. The AT45DB321 is enabled through the chip

select pin (CS) and accessed via a three-wire interface

consisting of the Serial Input (SI), Serial Output (SO), and

the Serial Clock (SCK).

All programming cycles are self-timed, and no separate

erase cycle is required before programming.

Block Diagram

Memory Array

To provide optimal flexibility, the memory array of the

AT45DB321 is divided into three levels of granularity com-

prising of sectors, blocks, and pages. The Memory Archi-

tecture Diagram illustrates the breakdown of each level and

details the number of pages per sector and block. All pro-

gram operations to the DataFlash occur on a page by page

basis; however, the optional erase operations can be per-

formed at the block or page level.

FLASH MEMORY ARRAY

PAGE (528 BYTES)

BUFFER 2 (528 BYTES)

BUFFER 1 (528 BYTES)

I/O INTERFACE

SCK

CS

RESET

GND

RDY/BUSY

WP

SO

SI