AT45DB321

4

MAIN MEMORY PAGE TO BUFFER TRANSFER: A page

of data can be transferred from the main memory to either

buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and

55H for buffer 2, is followed by one reserved bit, 13

address bits (PA12-PA0) which specify the page in main

memory that is to be transferred, and 10 don’t care bits.

The CS pin must be low while toggling the SCK pin to load

the opcode, the address bits, and the don’t care bits from

the SI pin. The transfer of the page of data from the main

memory to the buffer will begin when the CS pin transitions

from a low to a high state. During the transfer of a page of

data (t

whether the transfer has been completed or not.

MAIN MEMORY PAGE TO BUFFER COMPARE: A page of

data in main memory can be compared to the data in buffer

1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and 61H for

buffer 2, is followed by 24 address bits consisting of one

reserved bit, 13 address bits (PA12-PA0) which specify the

page in the main memory that is to be compared to the

buffer, and 10 don't care bits. The loading of the opcode

and the address bits is the same as described previously.

The CS pin must be low while toggling the SCK pin to load

the opcode, the address bits, and the don't care bits from

the SI pin. On the low to high transition of the CS pin, the

528 bytes in the selected main memory page will be com-

pared with the 528 bytes in buffer 1 or buffer 2. During this

time (t

busy. On completion of the compare operation, bit 6 of the

status register is updated with the result of the compare.

Program

BUFFER WRITE: Data can be shifted in from the SI pin

into either buffer 1 or buffer 2. To load data into either

buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,

is followed by 14 don't care bits and 10 address bits (BFA9-

BFA0). The 10 address bits specify the first byte in the

buffer to be written. The data is entered following the

address bits. If the end of the data buffer is reached, the

device will wrap around back to the beginning of the buffer.

Data will continue to be loaded into the buffer until a low to

high transition is detected on the CS pin.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH

BUILT-IN ERASE: Data written into either buffer 1 or buffer

2 can be programmed into the main memory. An 8-bit

opcode, 83H for buffer 1 or 86H for buffer 2, is followed by

one reserved bit, 13 address bits (PA12-PA0) that specify

the page in the main memory to be written, and 10 addi-

tional don't care bits. When a low to high transition occurs

on the CS pin, the part will first erase the selected page in

main memory to all 1s and then program the data stored in

the buffer into the specified page in the main memory. Both

the erase and the programming of the page are internally

self timed and should take place in a maximum time of t

During this time, the status register will indicate that the

part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-

OUT BUILT-IN ERASE: A previously erased page within

main memory can be programmed with the contents of

either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1

or 89H for buffer 2, is followed by one reserved bit, 13

address bits (PA12-PA0) that specify the page in the main

memory to be written, and 10 additional don’t care bits.

When a low to high transition occurs on the CS pin, the part

will program the data stored in the buffer into the specified

page in the main memory. It is necessary that the page in

main memory that is being programmed has been previ-

ously erased. The programming of the page is internally

During this time, the status register will indicate that the

part is busy.

PAGE ERASE: The optional Page Erase command can be

used to individually erase any page in the main memory

array allowing the Buffer to Main Memory Page Program

without Built-In Erase command to be utilized at a later

time. To perform a Page Erase, an opcode of 81H must be

loaded into the device, followed by one reserved bit, 13

address bits (PA12-PA0), and 10 don’t care bits. The 13

address bits are used to specify which page of the memory

array is to be erased. When a low to high transition occurs

on the CS pin, the part will erase the selected page to 1s.

The erase operation is internally self-timed and should take

place in a maximum time of t

register will indicate that the part is busy.

BLOCK ERASE: A block of eight pages can be erased at

one time allowing the Buffer to Main Memory Page Pro-

gram without Built-In Erase command to be utilized to

reduce programming times when writing large amounts of

data to the device. To perform a Block Erase, an opcode of

50H must be loaded into the device, followed by one

reserved bit, 10 address bits (PA12-PA3), and 13 don’t

care bits. The 10 address bits are used to specify which

block of eight pages is to be erased. When a low to high

transition occurs on the CS pin, the part will erase the

selected block of eight pages to 1s. The erase operation is

internally self-timed and should take place in a maximum

time of t

that the part is busy.